A Memory and Performance Optimized Architecture of Deblocking Filter in H.264/AVC

Min, Kyeong-Yuk; Chong, Jong‐Wha

doi:10.1109/mue.2007.21

Cited by 17 publications

(10 citation statements)

References 3 publications

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“…A major effort has been spent on individual blocks of the H.264 codec e.g. DCT ( [33][34][35]) ME ( [36][37][38][39]), and De-blocking Filter ( [40][41][42][43][44]). Instead of targeting one specific component, we have implemented 12 hardware accelerators (see Section 3) for the major computationalintensive parts of the H.264 encoder and used them for evaluating our proposed application structure in the result section.…”

Section: Related Workmentioning

confidence: 99%

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Optimizing the H.264/AVC Video Encoder Application Structure for Reconfigurable and Application-Specific Platforms

Shafique¹,

Bauer²,

Henkel³

2008

J Sign Process Syst

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The H.264/AVC video coding standard features diverse computational hot spots that need to be accelerated to cope with the significantly increased complexity compared to previous standards. In this paper, we propose an optimized application structure (i.e. the arrangement of functional components of an application determining the data flow properties) for the H.264 encoder which is suitable for application-specific and reconfigurable hardware platforms. Our proposed application structural optimization for the computational reduction of the Motion Compensated Interpolation is independent of the actual hardware platform that is used for execution. For a MIPS processor we achieve an average speedup of approximately 60× for Motion Compensated Interpolation. Our proposed application structure reduces the overhead for Reconfigurable Platforms by distributing the actual hardware requirements amongst the functional blocks. This increases the amount of available reconfigurable hardware per Special Instruction (within a functional block) which leads to a 2.84× performance improvement of the complete encoder when compared to a Benchmark Application with standard optimizations. We evaluate our application structure by means of four different hardware platforms.

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Section: Related Workmentioning

confidence: 99%

“…[40] uses a 2×4×4 internal buffer and 32×16 internal SRAM for buffering operation of Deblocking Filter with I/O bandwidth of 32-bits. All filtering options are calculated in parallel while the condition computation is done in a control unit.…”

Section: Related Workmentioning

confidence: 99%

Optimizing the H.264/AVC Video Encoder Application Structure for Reconfigurable and Application-Specific Platforms

Shafique¹,

Bauer²,

Henkel³

2008

J Sign Process Syst

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“…This approach provides better data reuse than one dimensional filtering and pixels are written earlier to the main memory. In [8][9][10], two-dimensional filtering order is used by alternating horizontal filtering and vertical filtering on the block, and local buffer size is reduced. In [7], [11][12][13], the pipelined filter design offers advantages of reducing the critical path of the design, increasing the clock speed, and reducing latency.…”

Section: Introductionmentioning

confidence: 99%

A Bit-Rate Aware Scalable H.264/AVC Deblocking Filter Using Dynamic Partial Reconfiguration

Khraisha

Lee

2011

J Sign Process Syst

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In H.264/AVC, a deblocking filter improves visual quality by reducing the presence of blocking artifacts in decoded video frames. The deblocking filter accounts for one third of the computational complexity of the decoder. This paper exploits the scalability on the hardware and the algorithmic level to synergize the performance and to reduce the computational complexity. First, we propose a modular deblocking filter architecture which can be scaled to adapt to the required computing capability for various bit-rates, resolutions, and frame rate of video sequences. The scalable architecture is based on FPGA using dynamic partial reconfiguration. This desirable feature of FPGAs makes it possible for different hardware configurations to be implemented during run-time. The proposed design can be scaled to filter up to four different edges simultaneously, resulting in significant reduction of total processing time. Secondly, our experiments show that significant reduction in computational complexity can be achieved by the increased presence of skipped macroblocks at lower bitrates, thus, avoiding redundant filtering operations. The implemented architecture is evaluated using the Xilinx Virtex-4 ML410 FPGA board. The design operates at a maximum frequency of 103 MHz. The reconfiguration is done through Internal Configuration Access Port (ICAP) to achieve maximum performance needed by real time applications.

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“…Previous research of fast deblocking filter focuses on two fields: pure software implementations [1][2] and hardware implementations [3][4][5][6][7][8][9][10][11] . The complexity of the filter is mainly due to the high adaptivity that leads to a lot of conditional computations that are executed in the inner loop of the algorithm which occupies about 30% to 90% of the overall computation time [3] .…”

Section: Introductionmentioning

confidence: 99%

“…In Refs. [4][5][7][8], the advanced 2D processing orders are proposed which reduced operation cycles and memory accesses. In Refs.…”

Section: Introductionmentioning

confidence: 99%

Parallel-pipelined architecture of H.264 deblocking filter with adaptive dynamic power

Lin

2010

J. Shanghai Jiaotong Univ. (Sci.)

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In H.264, the computational complexity and memory access of deblocking filter are variable and depend on the video contents. In this paper, a pipelined VLSI architecture of deblocking filter with adaptive dynamic power is proposed. It avoids redundant computations and memory access by precluding the blocks which can be skipped. And the vertical and horizontal edges are simultaneously processed in an advanced scan order to speed up the decoder. As a result, the dynamic power of the proposed architecture can be reduced (up to about 89%) adaptively for different videos. And the off-chip memory access is improved compared to the previous designs. Moreover, the processing capability of the proposed architecture is very appropriate for real-time deblocking of high-definition television (HDTV, 1 920× 1 080 pixel/frame, 30 frame/s video signals) video operation at 38 MHz, which significantly outperforms the previous designs from 1.25 times to 4.8 times.

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A Memory and Performance Optimized Architecture of Deblocking Filter in H.264/AVC

Cited by 17 publications

References 3 publications

Optimizing the H.264/AVC Video Encoder Application Structure for Reconfigurable and Application-Specific Platforms

Optimizing the H.264/AVC Video Encoder Application Structure for Reconfigurable and Application-Specific Platforms

A Bit-Rate Aware Scalable H.264/AVC Deblocking Filter Using Dynamic Partial Reconfiguration

Parallel-pipelined architecture of H.264 deblocking filter with adaptive dynamic power

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