A memory-efficient realization of cyclic convolution and its application to discrete cosine transform

Abstract

This paper presents a memory-efficient approach to realize the cyclic convolution and its application to the discrete cosine transform (DCT). We adopt the way of distributed arithmetic (DA) computation, exploit the symmetry property of DCT coefficients to merge the elements in the matrix of DCT kernel, separate the kernel to be two perfect cyclic forms, and partition the content of ROM into groups to facilitate an efficient realization of a one-dimensional (1-D) -point DCT kernel using ( -1)/2 adders or substractors, one small ROM module, a barrel shifter, and (( 1) 2) + 1 accumulators. The proposed memory-efficient design technique is characterized by rearranging the content of the ROM using the conventional DA approach into several groups such that all the elements in a group can be accessed simultaneously in accumulating all the DCT outputs for increasing the ROM utilization. Considering an example using 16-bit coefficients, the proposed design can save more than 57% of the delayarea product, as compare with the existing DA-based designs in the case of the 1-D seven-point DCT. Finally, a 1-D DCT chip was implemented to illustrate the efficiency associated with the proposed approach.

The Algorithm and Structure for Digital Normalized Cross-Correlation by Using First-Order Moment

“…The proposed structure's hardware complexity is dependent upon L. Furthermore, for long NCCs, or two-dimension NCCs when N and P are larger than L, the adder number of the proposed structure is lower than that of the structure [22], and the latency of the proposed structure is lower than that of the structure [33]. Figure 12 shows the three structures' adder number and latency increasing along with N, where the proposed structure adopts maximum adder and latency to perform comparisons.…”

“…Direct calculation 2N (N + 1) 3N (N + 1) FFT-based algorithm [8,9] (3/2) Nlog 2 N − (3/2) N + 16 (7/2) Nlog 2 N − N/2 + 15 DA-based algorithm [22] 7N − 1 (5N − 2) log 2 L + 8N − 1 Fast NCC algorithm [15] 0 3N (N + 1) The proposed algorithm 6N − 1 N (N + 5L/2 + 5) -4…”

“…Multiplication Addition Direct calculation 2N (N + 1) 3N (N + 1) FFT-based algorithm [8,9] (3/2) Nlog2N − (3/2) N + 16 (7/2) Nlog2N − N/2 + 15 DA-based algorithm [22] 7N − 1 (5N − 2) log2L + 8N − 1 Fast NCC algorithm [15] 0 3N (N + 1) The proposed algorithm 6N − 1 N (N + 5L/2 + 5) -4 (a) (b) The wireless sensor and communication is an important application field for the proposed algorithm. Therefore, we compare the execution time of the five algorithms from Table 1 by using a mobile phone with the type "HUAWEI nova 2s (HWI-AL00)" and the operation system "Android 9".…”

“…Table 2, it is an advantage that the proposed systolic structure does not need ROMs, while the other two structures use O(2 N ) ROMs that are hardware-expensive when N > 16. The structure [22] has minimum latency, but its throughput is more than 1. The structure [33] needs the O(P) adder and latency that would increase rapidly with N. In addition, it is important that the proposed algorithm has five advantages, as follows:…”

“…To hardware implementation of fast NCC, Very-Large-Scale Integration (VLSI) circuits have been applied, where systolic structures are popular due to their regularity and modularity [19][20][21]. The integration of the systolic array and the DA technique lead to more efficient VLSI implementation of cross-correlation, although they use many ROMs and address decoders [22,23]. The Residue Number System-based DA can reduce ROMs and enhance throughput, while extra encoding processes in the residue domain are necessary [24].…”