A Memory-Efficient TCAM Coprocessor for IPv4/IPv6 Routing Table Update

Kuo, Fang-Chen; Chang, Yeim-Kuan; Su, Cheng-Chien

doi:10.1109/tc.2013.22

Cited by 8 publications

(1 citation statement)

References 16 publications

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“…[1][2][3] Since the TCAM features super highspeed searching by parallel hardware processing, it is mainly used in mission-critical network routers for classifying fast packets. [4][5][6][7][8][9] Figure 1(a) shows a conventional TCAM cell with two 6-transistor static random access memory (6T-SRAM) cells in which the data comparator drives the common match line dynamically and the NOR-type match line sense amplifier (MLSA) detects whether the entry is matched or not. 10,11) Figure 1(b) shows a block diagram of the conventional TCAM.…”

Section: Introductionmentioning

confidence: 99%

Design and measurement of fully digital ternary content addressable memory using ratioless static random access memory cells and hierarchical-AND matching comparator

Nishikata¹,

Ali²,

Hosoda³

et al. 2018

Jpn. J. Appl. Phys.

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A 36-bit ' 32-entry fully digital ternary content addressable memory (TCAM) using the ratioless static random access memory (RL-SRAM) technology and fully complementary hierarchical-AND matching comparators (HAMCs) was developed. Since its fully complementary and digital operation enables the effect of device variabilities to be avoided, it can operate with a quite low supply voltage. A test chip incorporating a conventional TCAM and a proposed 24-transistor ratioless TCAM (RL-TCAM) cells and HAMCs was developed using a 0.18 µm CMOS process. The minimum operating voltage of 0.25 V of the developed RL-TCAM, which is less than half of that of the conventional TCAM, was measured via the conventional CMOS push-pull output buffers with the level-shifting and flipping technique using optimized pull-up voltage and resistors.

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