A memory mapping approach for network and controller optimization in parallel interleaver architectures

Abstract

Recent communication standards and storage systems uses parallel architectures for error correcting codes (LDPC or Turbocodes) to reliably transfer data between two equipments. However, parallel architectures suffer from memory access conflicts. In this paper, we present a method that finds a conflictfree memory mapping for any interleaving law and any parallelism. The proposed approach always complies with the interconnection network topology the designer wants to infer. Moreover, the resulting architecture is optimized by reducing the cost of network and controller (network and memory controller) architectures.