2015
DOI: 10.1016/j.scriptamat.2015.02.009
|View full text |Cite
|
Sign up to set email alerts
|

A metastable phase of tin in 3D integrated circuit solder microbumps

Abstract: A metastable phase of Sn has been found to co-exist with β-Sn in Pb-free SnAg microbumps in 3D integrated circuit technology. Synchrotron microbeam x-ray diffraction, high-resolution TEM imaging and selected-area electron diffraction were used to confirm the metastable phase, which has a orthorhombic lattice, with lattice parameter a = 0.635 nm, b = 0.639 nm, and c = 1.147 nm. Its composition is Sn containing a few percent of Ni. A higher rate of nucleation might have enabled its formation.

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1
1
1

Citation Types

0
9
0

Year Published

2016
2016
2024
2024

Publication Types

Select...
8

Relationship

0
8

Authors

Journals

citations
Cited by 20 publications
(9 citation statements)
references
References 9 publications
(9 reference statements)
0
9
0
Order By: Relevance
“…However, underfill entrapment caused by both capillary force and pre-applied underfill may influence microbumps reliability. Liu et al [ 63 ] emphasized that there must not be any filler trapped in the extrusion of the compressed microbumps, otherwise they will exhibit poor electrical conduction. Ohyama et al [ 62 ] overcame these challenges by employing a hybrid bonding process, whereby the excess pre-applied underfill-coated microbumps are removed by polishing.…”
Section: Three-dimensional Integrated Circuits: the Technologymentioning
confidence: 99%
“…However, underfill entrapment caused by both capillary force and pre-applied underfill may influence microbumps reliability. Liu et al [ 63 ] emphasized that there must not be any filler trapped in the extrusion of the compressed microbumps, otherwise they will exhibit poor electrical conduction. Ohyama et al [ 62 ] overcame these challenges by employing a hybrid bonding process, whereby the excess pre-applied underfill-coated microbumps are removed by polishing.…”
Section: Three-dimensional Integrated Circuits: the Technologymentioning
confidence: 99%
“…The signal of Sn was at 3.44 keV, which could serve as proof of the presence of Sn on the Sn/rGO/SPCE. 46 As shown in Table S1, an average elemental composition of Sn/rGO/ SPCE suggested the existence of C, O, and Sn with weight percentages of 79, 18, and 3 wt %, respectively.…”
Section: Resultsmentioning
confidence: 92%
“…The EDX spectrum in Figure g reveals that the Sn/rGO/SPCE had well-defined elemental peaks for carbon at 0.27 keV and oxygen at 0.52 keV, confirming the elemental component of the Sn/rGO catalyst ink. The signal of Sn was at 3.44 keV, which could serve as proof of the presence of Sn on the Sn/rGO/SPCE . As shown in Table S1, an average elemental composition of Sn/rGO/SPCE suggested the existence of C, O, and Sn with weight percentages of 79, 18, and 3 wt %, respectively.…”
Section: Results and Discussionmentioning
confidence: 99%
“…Based on annual report of SIA in 2005 that there are more transistors are produced with cost lower than a grain rice [20]. A history analyst, Gordon Moore, estimates that the amount of transistor in a chip will rise exponentially [21][22][23][24]. In Figure 4 it is shown the development of transistor inside a chip.…”
Section: Discussionmentioning
confidence: 99%
“…Based on Moore's law, miniaturization is approaching the limit and is now already to be used in nanoscale dimension. One way to overcome this limit is to combine the chip technology with a packaging technology that can accumulate chips into 3D integrated chips [22] [32][33]. When the dimension of IC became smaller electrical resistance, power density and thermal of the chips increase [34].…”
Section: The Present and The Futurementioning
confidence: 99%