A Method for Compression of Intra-Cortically-Recorded Neural Signals Dedicated to Implantable Brain–Machine Interfaces

Shaeri, MohammadAli; Sodagar, Amir M.

doi:10.1109/tnsre.2014.2355139

Cited by 31 publications

(10 citation statements)

References 24 publications

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“…Compared with the works of Karkare et al 16 and Yang et al 9 , the memory space required to implement the on-implant OSS proposed in this work is 5 times and 68 times smaller, respectively. In total, the on-implant O.S.S in this work is implemented using 1869 transistors per channel and takes a chip area of 0.0066 mm 2 ch: in a 130-nm CMOS process. This is while the former work 16 and the latter work 9 occupy 0.077 mm 2 ch: and 0.023 mm 2 ch: in 65 and 130 nm CMOS technologies, respectively.…”

Section: Resultsmentioning

confidence: 99%

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A framework for on-implant spike sorting based on salient feature selection

Shaeri

Sodagar

2020

Nat Commun

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On-implant spike sorting methods employ static feature extraction/selection techniques to minimize the hardware cost. Here we propose a novel framework for real-time spike sorting based on dynamic selection of features. We select salient features that maximize the geometric-mean of between-class distances as well as the associated homogeneity index effectively to best discriminate spikes for classification. Wave-shape classification is performed based on a multi-label window discrimination approach. An external module calculates the salient features and discrimination windows through optimizing a replica of the onimplant operation, and then configures the on-implant spike sorter for real-time online operation. Hardware implementation of the on-implant online spike sorter for 512 channels of concurrent extra-cellular neural signals is reported, with an average classification accuracy of 88%. Compared with other similar methods, our method shows reduction in classification error by a factor of~2, and also reduction in the required memory space by a factor of~5.

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Section: Resultsmentioning

confidence: 99%

“…In total, the on-implant O.S.S in this work is implemented using 1869 transistors per channel and takes a chip area of 0.0066 mm 2 ch: in a 130-nm CMOS process. This is while the former work 16 and the latter work 9 occupy 0.077 mm 2 ch: and 0.023 mm 2 ch: in 65 and 130 nm CMOS technologies, respectively.…”

Section: Resultsmentioning

confidence: 99%

A framework for on-implant spike sorting based on salient feature selection

Shaeri

Sodagar

2020

Nat Commun

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“…1. This decomposition of the input signal allows studying each frequency component with a resolution matched to its scale and investigated in the data compression [11], [12]. DWT with Haar basis function is used in this study because it is less complex and gives good performance.…”

Section: B Discrete Wavelet Transform (Dwt)mentioning

confidence: 99%

Hybrid Compression Techniques for EEG Data Based on Lossy/Lossless Compression Algorithms

Alsenwi¹,

Ismail²,

Darweesh³

2018

Preprint

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The recorded Electroencephalography (EEG) data comes with a large size due to the high sampling rate. Therefore, large space and more bandwidth are required for storing and transmitting the EEG data. Thus, preprocessing and compressing the EEG data is a very important part in order to transmit and store it efficiently with fewer bandwidth and less space. The objective of this paper is to develop an efficient system for EEG data compression. In this system, the recorded EEG data are firstly preprocessed in the preprocessing unit. Standardization and segmentation of EEG data are done in this unit. Then, the resulting EEG data are passed to the compression unite. The compression unit composes of a lossy compression algorithm followed by a lossless compression algorithm. The lossy compression algorithm transforms the randomness EEG data into data with high redundancy. Subsequently, A lossless compression algorithm is added to investigate the high redundancy of the resulting data to get high Compression Ratio (CR) without any additional loss. In this paper, the Discrete Cosine Transform (DCT) and Discrete Wavelet Transform (DWT) are proposed as a lossy compression algorithms. Furthermore, Arithmetic Encoding and Run Length Encoding (RLE) are proposed as a lossless compression algorithms. We calculate the total compression and reconstruction time (T), Root Mean Square Error (RMSE), and CR in order to evaluate the proposed system. Simulation results show that adding RLE after the DCT algorithm gives the best performance in terms of compression ratio and complexity. Using the DCT as a lossy compression algorithm followed by the RLE as a lossless compression algorithm gives CR = 90% at RM SE = 0.14 and more than 95% of CR at RM SE = 0.2.

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“…1 However, as a technical challenge, volume of the recorded data will consequently be too large to handle from the standpoint of system implementation constraints. [6][7][8] Recently, some other techniques have been proposed and used for the spatial compression of neural signals, namely, compressive sensing methods 9 and inpainting-based compression. This includes spike processing techniques (eg, spike detection, 2 spike extraction, 3 and spike feature extraction 4 ), hardware-embedded processing methods (eg, analog/digital conversion with antilogarithmic quantization 5 ), and transform-based signal processing approaches such as wavelet and Walsh-Hadamard transforms.…”

Section: Introductionmentioning

confidence: 99%

“…This includes spike processing techniques (eg, spike detection, 2 spike extraction, 3 and spike feature extraction 4 ), hardware-embedded processing methods (eg, analog/digital conversion with antilogarithmic quantization 5 ), and transform-based signal processing approaches such as wavelet and Walsh-Hadamard transforms. [6][7][8] Recently, some other techniques have been proposed and used for the spatial compression of neural signals, namely, compressive sensing methods 9 and inpainting-based compression. 10 It is a known fact that in intracortical single-unit recording, high spatial resolution is achieved at the price of some extent of redundancy in the recorded neuronal activities.…”

Section: Introductionmentioning

confidence: 99%

A modified whitening transform for the reduction of spatial data redundancy in multichannel neural recording implants

Yazdani

Rashidi

Sodagar

2018

Circuit Theory & Apps

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This paper proposes an approach for the reduction of redundant spatial information recorded by implantable high-density neural recording microsystems. To realize the proposed approach, a modified whitening transform is introduced, which is efficient enough (in hardware implementation) to comply with the hardware design constraints associated with implantable microsystems. Based on the proposed approach, a 32-channel processor is designed, prototyped, and tested for a library of both pre-recorded and synthesized multichannel single-unit neural signals. Designed in a 0.18-μm standard CMOS technology, the processor occupies 0.3 mm 2 of silicon area and consumes 238 μW @1.8 V/1.28 MHz.

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A Method for Compression of Intra-Cortically-Recorded Neural Signals Dedicated to Implantable Brain–Machine Interfaces

Cited by 31 publications

References 24 publications

A framework for on-implant spike sorting based on salient feature selection

A framework for on-implant spike sorting based on salient feature selection

Hybrid Compression Techniques for EEG Data Based on Lossy/Lossless Compression Algorithms

A modified whitening transform for the reduction of spatial data redundancy in multichannel neural recording implants

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