A method for fast jitter tolerance analysis of high-speed PLLs

Abstract

We propose a fast method for identifying the jitter tolerance curves of high-speed phase locked loops. The method is based on an adaptive recursion and uses known tail fitting methods to realize a fast optimization combined with a small number of jitter samples. It allows for efficient behavioral simulations, and can also be applied to hardware measurements. A typical modeling example demonstrates applicability to both software and hardware scenarios and achieves simulated measurement times in the range of few hundred milliseconds.

Multi-data rate receiver for high-speed serial interfaces

“…High speed link transceivers jitter performance verification, requires system modelling in high level description languages like Verilog-AMS, verilog-A [59] or similar in order to: a) be able to implement and easily parameterize the jitter noise sources, b) speed up the verification simulations, c) co-simulate both transistor level building blocks and behavioural modules, d) generate the desired metrics, like jitter tolerance mask or BER [60] and e) accelerate the circuit design process. There are several published works which implement the jitter behavioral modelling of HSSI's building blocks employing verilog-AMS, such as the digital clock and data recovery circuit presented in [61] and high speed phase-locked loop presented in [62], [154].…”