A method for hardware software partitioning

Barros, Edna

doi:10.1109/cmpeur.1992.218469

Cited by 26 publications

(6 citation statements)

References 4 publications

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“…The nodes in the TCS include linear distortion filter, Gaussian noise generator, harmonic generator, etc. In the modem and TCS examples considered, the DAGs consist of 27 and 15 nodes respectively 8 .…”

Section: Practical Examplesmentioning

confidence: 99%

The Extended Partitioning Problem: Hardware/Software Mapping, Scheduling, and Implementation-bin Selection

Kalavade

LEE

2002

Readings in Hardware/Software Co-Design

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Section: Practical Examplesmentioning

confidence: 99%

The Extended Partitioning Problem: Hardware/Software Mapping, Scheduling, and Implementation-bin Selection

Kalavade

LEE

2002

Readings in Hardware/Software Co-Design

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“…The partitioning problem has been broached, though somewhat less successfully so far, for hardware/software codesign [Gup92] [Hen93] [Bar92]. We have been investigating the partitioning problem for hardware/software codesign by concentrating on the synchronous dataflow (SDF) model of computation [Lee87].…”

Section: Partitioningmentioning

confidence: 99%

Manifestations of heterogeneity in hardware/software co-design

Kalavadee

Lee

1994

Proceedings of the 31st Annual Conference on Design Automation Conference - DAC '94

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We identify three distinct types of hardware/software codesign:1. Joint design of an instruction-set architecture and its program. 2. Synthesis of hardware and/or software from a common specification.3. Specification, synthesis, and simulation of heterogeneous systems.These can be viewed as manifestations of heterogeneity in the design methodology.The first type concerns the joint synthesis of a data-path and its controller, two conceptually distinct parts of a processor [Pau93]. The heterogeneity in this approach is limited to distinguishing the datapath from its controller.In type 2, a unified representation of an application is mapped into some mixture of implementation technologies. For example, a dataflow graph could be partitioned, and the separate partitions could be fed to hardware and software synthesis tools [Kal93]. The software components execute on commodity processors, or possibly on processors synthesized as in type 1. A hierarchical finite state machine could also be converted to hardware or software implementations [Har90]. If concurrent FSMs are used, then a mixture of hardware implementations might be attractive. In type 2, the heterogeneity is limited to distinguishing implementation technologies; the model of computation is unified.In type 3, the design representation need not be unified. Distinct models of computation can be used for different parts of the design. The model of computation for each component would be chosen on the basis of the properties of that component. For instance, dataflow would be used for signal processing, and hierarchical FSMs for control. A typical application could combine both models of computation. Within each model of computation, types 1 or 2 might apply in synthesizing the implementations.Type 3 addresses a large cross section of system-level design problems. In the signal processing domain, for example, most applications combine some hard-real-time numerical processing of signals with much more dynamic control. In applications such as modems, wireless communication systems, video phones, voice mail systems, voice recognition systems, disk-drive controllers, and data compression, one or more signal processing kernels are invoked in response to outside stimuli. For example, a modem needs to negotiate a common transmission format with another modem when a connection is established, or when a wireless device moves from one service area to another. System-Level DesignType 1 is fundamentally still a chip-level design problem. It can be viewed as an approach to high-level synthesis. In this paper, we concentrate on system-level problems, and hence on types 2 and 3. In this context, four key problems emerge:• partitioning Even a unified model such as SDF does not preclude a bias towards one type of implementation or another. Certain properties of a graph lead to a preference:• the mix of operations,• the speed requirements,• the regularity of the graph,• the parallelism in the graph,• the word length requirements, and• the need for programmability.In the last of th...

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“…The quality of the partitioning in CODES therefore depends on the quality of the system model, and the experience of the designers. We have tested several academic approaches to partitioning, such a s the one described in [ 3 ] , but none of them W;LX mature enough to integrate it into CODES.…”

Section: Component Design and System Integrationmentioning

confidence: 99%