A Method for Leakage Current and Power Reduction of Buffer in 65-nm CMOS Technology Based on the Pileup-Effect

Abstract

In small-size Complementary Metal Oxide Semiconductor (CMOS) technology, the size of Very Large-Scale Integration (VLSI) below 90nm becomes higher and higher due to the enhancement of the short channel effect of transistors. CMOS Buffer is a very common circuit unit in VLSI. In this paper, a Pileup effect transistor (PET) is proposed to reduce the subthreshold leakage current of the CMOS buffer. The main principle of PET technology is to reduce the voltage difference between gate and source and the voltage difference between drain and source by lowering the voltage of source so as to reduce the subthreshold leakage current. Through simulation-based on Cadence and Taiwan Semiconductor Manufacturing Company (TSMC) N65 library, PET technology can reduce leakage current power consumption by about one-twelfth of the original while maintaining the function of the original CMOS buffer. PET technology has also been found to reduce current consumption in the transition state by about 40%.