A method of &amp;#x201C;chemical flip-chip bonding&amp;#x201D; without loading and heating for ultra-fine chip-to-substrate interconnects

Yokoshima, Tokihiko; Yamaji, Youhei; Kikuchi, Katsuya; Nakagawa, Hiroshi; Aoyagi, Masahiro

doi:10.1109/ectc.2009.5074000

Cited by 5 publications

(3 citation statements)

References 12 publications

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“…iii) Conventional flip-chip bonding. Reproduced from (Yokoshima et al, 2009), with permission from IEEE. iv) Two conformable arrays bonded by MCP.…”

Section: Interconnections and Connection Strategiesmentioning

confidence: 99%

Hybrid neuroelectronics: towards a solution-centric way of thinking about complex problems in neurostimulation tools

Drakopoulou,

Varkevisser,

Sohail

et al. 2023

Front.Electron.

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Responsive neuromodulation is increasingly being used to treat patients with neuropsychiatric diseases. Yet, inefficient bridges between traditional and new materials and technological innovations impede advancements in neurostimulation tools. Signaling in the brain is accomplished predominantly by ion flux rather than the movement of electrons. However, the status quo for the acquisition of neural signals is using materials, such as noble metals, that can only interact with electrons. As a result, ions accumulate at the biotic/abiotic interface, creating a double-layer capacitance that increases impedance and negatively impacts the efficiency of neural interrogation. Alternative materials, such as conducting polymers, allow ion penetration in the matrix, creating a volumetric capacitor (two orders of magnitude larger than an area-dependent capacitor) that lowers the impedance and increases the spatiotemporal resolution of the recording/stimulation. On the other hand, the increased development and integration capabilities of CMOS-based back-end electronics have enabled the creation of increasingly powerful and energy-efficient microchips. These include stimulation and recording systems-on-a-chip (SoCs) with up to tens of thousands of channels, fully integrated circuitry for stimulation, signal conditioning, digitation, wireless power and data telemetry, and on-chip signal processing. Here, we aim to compile information on the best component for each building block and try to strengthen the vision that bridges the gap among various materials and technologies in an effort to advance neurostimulation tools and promote a solution-centric way of considering their complex problems.

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“…iii) Conventional flip-chip bonding. Reproduced from (Yokoshima et al, 2009), with permission from IEEE. iv) Two conformable arrays bonded by MCP.…”

Section: Interconnections and Connection Strategiesmentioning

confidence: 99%

Hybrid neuroelectronics: towards a solution-centric way of thinking about complex problems in neurostimulation tools

Drakopoulou,

Varkevisser,

Sohail

et al. 2023

Front.Electron.

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“…The specific items include the following. Elemental technologies for chip stacking process are the following: low-volume, lowresistance, and low internal stress TSV structure using low-k organic insulator; [17] micro-pitch, high-density, and micro-bump connection formed by a thermo-compression method using cone-shaped micro-bumps; [18]- [20] electroless plating connection for power source pads where the power source pad electrodes are connected by direct Ni-B and Au electroless plating after chip stacking; [21] [22] interposer with passive components where the thin film capacitors or the chip capacitors are embedded in the substrate; [23] [24] and others. Evaluation and inspection technologies are as follows: evaluation of electrical property in local fine structures using high-speed sharp step signals with 10-ps rising time; [25] evaluation of 20 Gbps high-speed digital signal transmission; [26] evaluation of power supply wiring impedance using impedance analyzer for 10 Hz -40 GHz super-wide bandwidth; [27] inspection of good chips where electrical testing can be done at chip level using the membrane fine pitch contact probe; [28] boundary scan embedded test circuit where total electrical connection test of fine interconnects can be conducted after stacking; [29] high-speed inspection of coneshape micro-bumps where wafer level shape optical inspection can be conducted by laser illumination and high-speed highresolution image sensors; [30] and others.…”

Section: Elemental Technologies For the Manufacturing Process Of The mentioning

confidence: 99%

Developing a leading practical application for 3D IC chip stacking technology

Aoyagi

Imura

Kato

et al. 2016

Synthesiology English edition

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IC technologies, and the attempt to increase the integration density seemed to face the limit. The three-dimensional IC chip stacking technology whereby the IC devices are stacked vertically and packaged is one of the solutions, and expectation for it is rising recently as a technology for semiconductor device stacking that enables the increase of integration density for semiconductor ICs. Therefore, we established the fundamental technology for high-density high-integration electronic hardware construction required for 3D IC chip stacking, and we are working on the R&D of the application phase to create the flow of application system development, while engaging in technical support of massproduction technology that, in practice, should be undertaken by leading companies. Advancement of electronic hardware system integration technology by 3D IC chip stacking and the goal of this researchFirst, we shall review the recent development trends of the electronic hardware system integration technology that advanced the manufacturing technology in response to the demand for high density and high integration to enhance the system performance. The system integration method called the system in package (SIP) Term 1 is gaining attention, where several IC chips are stacked in a semiconductor IC package to integrate them into a certain size electronic system. This method enables stacking in the vertical direction that is different from the planar integration technology of -How to progress from fundamental technology to application technology-3D IC chip stacking technology, which is a technology to vertically stack multiple IC chips such as CMOS, MEMS and power IC chips, is expected to be one of future electronic device integration technologies, because integration along the additional vertical dimension affords efficient use of space and innovation of system architecture. We developed fundamental technology of high density integration for 3D IC chip stacking. To accelerate industrial applications of this technology, a mass-production process was developed in collaboration with a manufacturing equipment company.Research paper : Developing a leading practical application for 3D IC chip stacking technology (M.AOYAGI et al.) − 2 − Authors Masahiro AOYAGI G r a d u a t e d f r o m t h e D e p a r t m e n t of Elect ronic Engineer ing, Facult y of E ng i n e e r i ng , Na goy a I n s t it u t e of Tech nolog y i n 1982. Joi ned t he Electrotechnical Laboratory, Agency of Industrial Science and Technology, Ministr y of Inter national Trade and Industry in 1982. Engaged in the R&D of integrated circuit and system for superconductor device, high-speed high-density packaging system tech nolog y, and others. Obt ained doctorate (Engineering) from the Nagoya

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“…チ高密度超多チャンネル微細バンプ接続 [18]- [20] 、チップ積層後の電源パッド電極間を直接めっき法で接続する電源パッド間ブリッジめっき接続 [21] [22] 、薄膜コンデンサおよびチップコンデンサを基板内に埋め込んだ受動部品内蔵インターポーザ [23] [24] 等、評価検査技術として、10 ps 高速立ち上がりステップ信号を用いた局所微細構造電気特性評価 [25] 、20 Gbps デジタル高速信号伝送評価 [26] 、10 Hz-40 GHz の超広帯域に対応したインピーダンスアナライザによる電源供給配線インピーダンス評価 [27] 、メンブレン微細ピッチコンタクトプローブによるチップレベルの電気検査が可能な良品チップ検査 [28] 、積層後に微細接続部の全数電気接続検査が可能なチップ間接続バウンダリスキャン検査 [29] 、レーザー照明と高速高精細画像センサーにより全数形状検査が可能な微細円錐バンプ高速検査 [30]…”

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Developing an application for 3D IC chip stacking technology

Aoyagi¹,

Imura²,

Kato³

et al. 2016

Synthesiology

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3D IC chip stacking technology is expected to be the future of electronic device integration technology, because integration along the additional dimension affords efficient use of space and improvement of system architecture. We developed fundamental technology of high density integration for 3D IC chip stacking. To facilitate applications of this technology, a mass-production process was developed in collaboration with a production system company.

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A method of “chemical flip-chip bonding” without loading and heating for ultra-fine chip-to-substrate interconnects

Cited by 5 publications

References 12 publications

Hybrid neuroelectronics: towards a solution-centric way of thinking about complex problems in neurostimulation tools

Hybrid neuroelectronics: towards a solution-centric way of thinking about complex problems in neurostimulation tools

Developing a leading practical application for 3D IC chip stacking technology

Developing an application for 3D IC chip stacking technology

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