A methodology for accurate assessment of soft-broken gate oxide leakage and the reliability of VLSI circuits

Mason, P.; Duca, Anton; Holder, C.H.; Alam, Muhammad Ashraful; Hwang, D.

doi:10.1109/relphy.2004.1315366

Cited by 10 publications

(7 citation statements)

References 8 publications

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“…It is reported under other aging mechanism such as TDDB, the leakage current can increase with time [21], which will lead to an I DDT increment accordingly. This does not appear in our I DDT measurements, indicating that NBTI is already the dominating aging mechanism in 90nm technology.…”

Section: Accelerated Aging Experiments and The Iddt Measurement Setupmentioning

confidence: 99%

Unit-Based Functional IDDT Testing for Aging Degradation Monitoring in a VLIW Processor

Zhao

Kerkhoff

2015

2015 Euromicro Conference on Digital System Design

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In this paper, functional unit-based I DDT testing has been applied for a 90nm VLIW processor to monitor its aging degradation. This technique can provide health data for reliability evaluation as used in e.g. prognostic software for lifetime prediction. The test-program development based on the architecture of a single DSP processor, as well as implementation of an accelerated test (AT) is investigated and I DDT measurement results are evaluated. It is found that decrements of peak I DDT values of crucial functional units inside the processor characterize the power-law degradation with the aging time. This is in coherence with the aging behaviour of (PMOS) transistors caused by Negative-Bias-Temperature-Instability (NBTI), thereby validating the feasibility of this technique in monitoring target-process aging degradation.

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Section: Accelerated Aging Experiments and The Iddt Measurement Setupmentioning

confidence: 99%

Unit-Based Functional IDDT Testing for Aging Degradation Monitoring in a VLIW Processor

Zhao

Kerkhoff

2015

2015 Euromicro Conference on Digital System Design

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“…In this section, we propose a method of characterizing NBTI degradation in SRAM arrays using leakage measurement (I DDQ ). A similar method of using I DDQ has been applied to characterize the TDDB of MOS-FET devices [20], but none of the previous works have discussed the possibility of using I DDQ as a measure of NBTI. We will first show how lifetime I DDQ 's are predicted and modeled, especially under process variation.…”

Section: Nbti Characterization In Sram Arraymentioning

confidence: 99%

“…However, in real field, there are number of other sources which degrade the device reliability such as HCI and TDDB. For example, due to TDDB degradation, I DDQ measurement can actually increase with time [20]. Under such assumption, overall I DDQ degradation at time t, I DDQ (t), considering these reliability factors can be expressed as follows, = I(0) + C NBT I t 1/6 + C T DDB (t) + ... (13) where ∆I() represents temporal change in I DDQ due to different reliability factors.…”

Section: Ddq Under Multiple Reliability Degradation Sourcesmentioning

confidence: 99%

Characterization of NBTI induced temporal performance degradation in nano-scale SRAM array using I<inf>DDQ</inf>

Kang

Alam

Roy

2007

2007 IEEE International Test Conference

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One of the major reliability concerns in nano-scale VLSI design is the time dependent Negative Bias Temperature Instability (NBTI) degradation. Due to the higher operating temperature and increasing vertical oxide field, threshold voltage (V t ) of PMOS transistors can increase with time under NBTI. In this paper, we examine the impact of NBTI degradation in memory elements of digital circuits, focusing on the conventional 6T SRAM array topology. Using an empirical NBTI model based on the reaction diffusion (RD) framework, we first examine the impact of NBTI degradation in critical performance parameters of SRAM array. These parameters include 1) static noise margin (SNM), 2) statistical READ & WRITE stability, and 3) standby leakage current (I DDQ ). We show that due to NBTI, read stability of SRAM cell degrades, while write stability and standby leakage improve with time. Furthermore, using specific time trend of I DDQ degradation, we proposed efficient characterization technique to predict the lifetime behavior of SRAM array under NBTI.

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“…However, it has not been realized that IDDQ can sense the time dependent degradation in an IC. Recently, a work by Mason et al [18] has shown that IDDQ can be used as a temporal signature of time dependent dielectric breakdown (TDDB). However, none of the previous works characterized circuit reliability under NBTI using IDDQ measurement.…”

Section: Introductionmentioning

confidence: 99%

Characterization and estimation of circuit reliability degradation under NBTI using on-line I_DDQmeasurement

Kang

Kim

Islam

et al. 2007

Proceedings of the 44th Annual Conference on Design Automation - DAC '07

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Negative bias temperature instability (NBTI) in MOSFETs is one of the major reliability challenges in nano-scale technology. This paper presents an efficient technique to characterize and estimate the lifetime circuit reliability under NBTI degradation. Unlike conventional approaches, where a representative f MAX (maximum operating frequency) measurement from timing critical circuitry is used, we propose to utilize the standby circuit leakage I DDQ as a metric to detect and characterize temporal NBTI degradation in digital circuits. Compared to the f MAX based approach, the proposed I DDQ based technique benefits from lower test cost and improved capability of estimating reliability of complex circuitries such as ALUs and SRAM arrays. We have derived an analytical expression for circuit I DDQ from the analytical PMOS Vt degradation model (∆Vt ∝ t 1/6 ). The proposed model is verified with measurement data obtained from a test chip fabricated in 130nm technology. Furthermore, we examine the possible applications of our proposed I DDQ based NBTI characterization. We show that the temporal degradation in static noise margin (SNM) of SRAM array and f MAX of random logic circuits are highly correlated to the I DDQ measurement, and this relationship can be used to predict long term circuit reliability.

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A methodology for accurate assessment of soft-broken gate oxide leakage and the reliability of VLSI circuits

Cited by 10 publications

References 8 publications

Unit-Based Functional IDDT Testing for Aging Degradation Monitoring in a VLIW Processor

Unit-Based Functional IDDT Testing for Aging Degradation Monitoring in a VLIW Processor

Characterization of NBTI induced temporal performance degradation in nano-scale SRAM array using I<inf>DDQ</inf>

Characterization and estimation of circuit reliability degradation under NBTI using on-line I_DDQmeasurement

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A methodology for accurate assessment of soft-broken gate oxide leakage and the reliability of VLSI circuits

Cited by 10 publications

References 8 publications

Unit-Based Functional IDDT Testing for Aging Degradation Monitoring in a VLIW Processor

Unit-Based Functional IDDT Testing for Aging Degradation Monitoring in a VLIW Processor

Characterization of NBTI induced temporal performance degradation in nano-scale SRAM array using I<inf>DDQ</inf>

Characterization and estimation of circuit reliability degradation under NBTI using on-line IDDQmeasurement

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Characterization and estimation of circuit reliability degradation under NBTI using on-line I_DDQmeasurement