A methodology for accurate performance evaluation in architecture exploration

Abstract

We present a system that automatically generates a cycle-accurate and bit-true Instruction Level Simulator (ILS) and a hardware implementation model given a description of a target processor. An ILS can be used to obtain a cycle count for a given program running on the target architecture, while the cycle length, die size, and power consumption can be obtained from the hardware implementation model. These figures allow us to accurately and rapidly evaluate target architectures within an architecture exploration methodology for system-level synthesis.In an architecture exploration scheme, both the ILS and the hardware model must be generated automatically, else a substantial programming and hardware design effort has to be expended in each design iteration. Our system uses the ISDL machine description language to support the automatic generation of the ILS and the hardware synthesis model, as well as other related tools.

C Compilers for ASIPs

“…Moreover, ISDL is used by the retargetable simulator generation system GENSIM and a synthesizable HDL code generator [96]. CSDL: The Computer System Description Language (CSDL) is actually a family of machine description languages for the Zephyr compiler environment [4].…”

Functional Verification of Programmable Embedded Architectures

“…For example, the HDL generator HGEN [30] uses ISDL description, and the synthesis tool GO [49] is based on nML. Structure-centric ADLs such as MIMOLA are suitable for hardware generation.…”

“…Instruction Set Description Language (ISDL) was developed at MIT and used by the Aviv compiler [120] and GENSIM simulator generator [30]. The problem of constraint modeling is avoided by ISDL with explicit specification.…”

Seas

“…This tuning is critical to the accuracy of the results. Several previous works focused on early system-level estimation of performance, area and power [2][3][4] [5]. These works are different from SEAS in many ways, but primarily in the level of input description which determines how early the estimations can be obtained.…”

“…In [4] the system power is estimated also based on the power of its hardware and software components, again assuming that a system specification is available. In [5] the system architecture and instruction set are generated automatically, and the area and timing are derived from its RTL-based hardware specification. In all these systems, the detailed system specification is required for any meaningful analysis.…”