A methodology of designing and optimising a 4-bit absolute-value detector for the application of Brain-computer Interface

Abstract

Digital integrated circuits perform logical operations through several modules composed of logic gates. As a common module in digital circuits, the absolute value detector is applied to compare the absolute value of two binary inputs and can be further used for data sorting and searching. In clinical medicine, the detector can receive biological data from the sensor and control the instrument on the operating table. A typical application is Brain-computer Interface (BCI). Therefore, the performance of detectors is significant to electronic devices like computers. The optimisation of detectors usually concentrates on their propagation delay and power consumption. But theoretical optimisation will inevitably use simple logic and have large fan-in, and it is difficult to be implemented in practice. Here we explore an alternative plan that is more convenient to be produced in the industry, which combines static complementary metal-oxide semiconductor (CMOS) technology and transmission gates. After gate sizing, the critical path calculates the propagation delay and energy based on the logical effort theory. Finally, the relationship between energy and delay is analysed by scaling the voltage supply and the minimum energy occurs when the delay grows to 1.5 times the minimum delay.