A Micro-Power EEG Acquisition SoC With Integrated Feature Extraction Processor for a Chronic Seizure Detection System

Abstract

This paper presents a low-power SoC that performs EEG acquisition and feature extraction required for continuous detection of seizure onset in epilepsy patients. The SoC corresponds to one EEG channel, and, depending on the patient, up to 18 channels may be worn to detect seizures as part of a chronic treatment system. The SoC integrates an instrumentation amplifier, ADC, and digital processor that streams features-vectors to a central device where seizure detection is performed via a machine-learning classifier. The instrumentation-amplifier uses chopper-stabilization in a topology that achieves high input-impedance and rejects large electrode-offsets while operating at 1 V; the ADC employs power-gating for low energy-per-conversion while using static-biasing for comparator precision; the EEG feature extraction processor employs low-power hardware whose parameters are determined through validation via patient data. The integration of sensing and local processing lowers system power by 14x by reducing the rate of wireless EEG data transmission. Feature vectors are derived at a rate of 0.5 Hz, and the complete one-channel SoC operates from a 1 V supply, consuming 9 J per feature vector.Index Terms-1/f noise, algorithm design and analysis, amplifiers, biomedical equipment, brain, choppers, digital signal processing, electroencephalography, low-noise amplifiers, low-power electronics.

Active Electrodes for Wearable EEG Acquisition: Review and Electronics Design Methodology

“…17b) is implemented by a cascade of multiple small capacitors that are sampled in alternating phases. In [54], another SC resistor, utilizing a series-to-parallel charge sharing scheme (Fig. 17c), improves its resistance by x10 to maximum 150GΩ.…”

Flexible, Scalable and Energy Efficient Bio-Signals Processing on the PULP Platform: A Case Study on Seizure Detection

“…the first solution. In [21], the authors reported a SoC that acquires up to 18-channel EEG signals with an instrumental amplifier and an ADC performs an on-chip feature extraction, and then, through a low-power parallel-serial interfaces, the feature vector is streamed to a central device where an SVM is employed for the classification.…”

“…It is possible to note that current embedded implementations are capable of managing up to 18 electrodes, leveraging fixed function ASICs or highly specialized architectures. It is worth noticing that the authors in [21] claim that it is possible to employ up to 18 EEG channels for the seizure detection application, but as the execution of the SVM on the SoC would lead to a significant increase of the system power, the classification is performed remotely; while in [12], an inflexible SVM hardware accelerator has been employed to allow real-time operation within the power budget. In contrast with the previously-presented solutions, exploiting an optimized near-threshold micro-architecture and the most advanced FD-SOI technology, the PULP platform allows achieving high performance and energy efficiency, coupled with the high versatility of programmable processors.…”

Feasibility of Successive Approximation Register ADC in Ultra Low Power Biomedical Applications

“…5. Energy saving capacitor array SAR ADC architecture [13] A system on chip has been proposed for the feature detection and to detect the onset of seizures of EEG channel and hence convert these analog EEG signals to digital domain in [14]. For feature vector streaming, the Instrumentation Amplifier (I-amp), which amplifies the 10-50 µV EEG Signal from the passive scalp electrodes, an ADC, a processor for feature extraction and a low power parallel-serial interface, has been integrated into a single central device.…”