A Microarchitecture Implementation Framework for Online Learning with Temporal Neural Networks

TNN7: A Custom Macro Suite for Implementing Highly Optimized Designs of Neuromorphic TNNs

“…In order to report the optimization gains presented in Section IV, following steps are adopted: 1) Genus is used to synthesize the original functional modules from [6] with the ASAP7 standard cell library and establish the baseline values; 2) TNN7 macro equivalent of the original modules are designed by either (i) structurally optimizing at the microarchitectural level, or (ii) creating mixed-signal circuits from scratch in Virtuoso; 3) Genus is used to resynthesize the modules by replacing the ASAP7 standard cells with the TNN7 .lib and .lef files (obtained from Liberate and Abstract), to obtain post-synthesis area, power and delay. These values are then compared against the ASAP7-based post-synthesis values to compute the corresponding improvements.…”

“…These features make TNNs truly neuromorphic and therefore suitable for building extremely energy-efficient edgenative sensory processors for applications such as time-series clustering [1]. A microarchitecture framework for efficient CMOS implementation of TNNs has recently been proposed in [6]. The proposed implementation methodology utilizes two notions of temporal resolution and thereby hardware clocks: 1) unit clock serving as the finest temporal resolution to calibrate the spike timings within a single instance of input, and 2) a coarser resolution gamma clock to separate different input instances.…”

“…The proposed implementation methodology utilizes two notions of temporal resolution and thereby hardware clocks: 1) unit clock serving as the finest temporal resolution to calibrate the spike timings within a single instance of input, and 2) a coarser resolution gamma clock to separate different input instances. The authors in [6] use standard off-the-shelf 45nm CMOS to implement the key TNN microarchitectural elements, namely, neurons, columns and STDP learning rules.…”

“…This paper builds on and goes beyond the work in [6], exploring the potential for creating a customized cell library that utilizes inherent TNN principles to improve the power, performance and area (PPA) of TNN designs. Furthermore, this work serves as the first step towards creating a scalable design framework and toolsuite for building TNN-based neuromorphic processors.…”

“…These macros (elaborated in Section III) are summarized in Table I along with their functional descriptions and schematic figure labels. It should be noted, these custom macros can be generalized beyond use in the microarchitecture model in [6], and can serve as the foundation for building generic temporal functions based on space-time algebra [8]. To the best of our knowledge, this is the first work that proposes custom macros for highly efficient scalable CMOS implementation of TNNs.…”