A Mini-MIPS microprocessor for adiabatic computing

Campos-Aguillón, César O.; Celis-Cordova, Rene; Hänninen, Ismo; Lent, Craig S.; Orlov, Alexei O.; Snider, Gregory L.

doi:10.1109/icrc.2016.7738678

Cited by 11 publications

(7 citation statements)

References 16 publications

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“…This approach can also be easily applied for other powerclocking schemes such as single-phase, 2-phase and Bennett clocking used in adiabatic logic designs. However, it will not be straightforward to deploy in 2-phase and Bennett clocking due to the long idle period for the former [23] and long hold and idle period for the later [31] power clocking scheme. A part of the VHDL description of the power-clock generation is shown in Fig.…”

Section: Modelling Trapezoidal Power-clockmentioning

confidence: 99%

Modelling, simulation and verification of 4-phase adiabatic logic design: A VHDL-Based approach

2019

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The design and functional verification of the 4-phase adiabatic logic implementation take longer due to the complexity of synchronizing the power-clock phases. Additionally, as the adiabatic system scales, the amount of time in debugging errors increases, thus, increasing the overall design and verification time. This paper proposes a VHDL-based modelling approach for speeding up the design and verification time of the 4-phase adiabatic logic systems. The proposed approach can detect the functional errors, allowing the designer to correct them at an early design stage, leading to substantial reduction of the design and debugging time. The originality of this approach lies in the realization of the trapezoidal power-clock using function declaration for the four periods namely; Evaluation (E), Hold (H), Recovery (R) and Idle (I) exclusively. The four periods are defined in a VHDL package followed by a library design which contains the behavioral VHDL model of adiabatic NOT/BUF logic gate. Finally, this library is used to model and verify the structural VHDL representations of the 4-phase 2-bit ringcounter and 3-bit up-down counter, as design examples to demonstrate the practicality of the proposed approach.

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Section: Modelling Trapezoidal Power-clockmentioning

confidence: 99%

Modelling, simulation and verification of 4-phase adiabatic logic design: A VHDL-Based approach

2019

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“…Adiabatic computing has been investigated as a path to lowpower complementary metal-oxide-semiconductor (CMOS) chips [1][2][3][4][5][6][7][8]. The literature shows the benefit of adiabatic circuits at the level of a single gate or a small, structured ensemble of gates organised conveniently for multiphase clocking.…”

Section: Introductionmentioning

confidence: 99%

“…We now review the principle behind adiabatic switching and then provide an outline of the paper. Conventional switching in a CMOS circuit with a supply of voltage drain drain (VDD) draws C L * VDD 2 joules from supply-dissipating half * C L * VDD 2 joules each during charging (output rising transition) and discharging (output falling transition that draws out all of the energy that was stored in C L during chargeup)-of the output node with capacitive load C L . The energy dissipated for each transition is half * C L * VDD 2 .…”

Section: Introductionmentioning

confidence: 99%

“…Conventional switching in a CMOS circuit with a supply of voltage drain drain (VDD) draws C L * VDD 2 joules from supply-dissipating half * C L * VDD 2 joules each during charging (output rising transition) and discharging (output falling transition that draws out all of the energy that was stored in C L during chargeup)-of the output node with capacitive load C L . The energy dissipated for each transition is half * C L * VDD 2 . Switching power reduction is practised widely today by avoiding overdesign (containing C L ) and/or reduced swing (power supply management).…”

Section: Introductionmentioning

confidence: 99%

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Challenges to adopting adiabatic circuits for systems‐on‐a‐chip

Rengarajan

Mondal

Kapre

2021

IET Circuits, Devices & Syst

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Adiabatic complementary metal-oxide-semiconductor (CMOS) circuits have been proposed as a low-power option for CMOS systems-on-a-chip (SoCs) but have not gained popularity due to practical difficulties in scaling to millions of gates. The architecture of a pipeline of stages with slow-transitioning clock phases demands the generation and distribution of clock phases precisely and efficiently. This power must be more than offset by the power saved by using adiabatic circuits. The problems in adiabatic logic circuits are described, and solutions are proposed to address them. Three published topologies are considered, namely positive-feedback adiabatic logic (PFAL), two-level adiabatic logic (2-LAL) and clocked adiabatic logic in 40 nm CMOS technology at 100 MHz. New circuit ideas for complete level restore in PFAL and avoidance of floating nodes in 2-LAL are presented. The problem with 2-LAL multi-input gates is published and solved for the first time here using a modified PFAL. The conclusion is that a 3X power savings in PFAL is about the best that can be achieved in an SoC context-a low return given the required investments in area and complexity. This should motivate the future discovery of more efficient solutions. This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

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“…58 But in any case, all logically reversible computations, since they cannot lose any information, must still always be designed with attention being paid at all times to where all of the information embedded in the computation is going. That essential new design constraint is why the field of reversible computing is unavoidably needed, and why we must eventually begin more widespread efforts to develop (and figure out practical, efficient ways to implement) reversible logic architectures 60 and algorithms. 61 Those of us who have been most deeply immersed in the foundations of this field have well understood all of these issues for a very long time.…”

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confidence: 99%

Back to the Future: The Case for Reversible Computing

Frank

2018

Preprint

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There is one, and only one way, consistent with fundamental physics, that the efficiency of general digital computation can continue increasing indefinitely, and that is to apply the principles of reversible computing. We need to begin intensive development work on this technology soon if we want to maintain advances in computing and the attendant economic growth NOTE: This paper is an extended author's preprint of the feature article titled "Throwing Computing Into Reverse" 1 (print) or "The Future of Computing Depends on Making it Reversible" 2 (online), published by IEEE Spectrum in Aug.-Sep. 2017. This preprint is based on the original draft manuscript that the author submitted to Spectrum, prior to IEEE edits and feedback from external readers.Since the dawn of the transistor, technologists, and the world at large, have grown accustomed to a steady trend of exponentially-improving performance for information technologies at any given cost level. This performance growth has been enabled by the underlying trend, described by Moore's Law, 3 of the exponentially-increasing number of electronic devices (such as transistors) that can be fabricated on an integrated circuit. According to the classic rules of semiconductor scaling, 4 as transistors were made smaller, they became simultaneously cheaper, faster, and more energy-efficient, a massive win-win-win scenario, which resulted in concordantly massive investments in the ongoing push to advance semiconductor fabrication technology to ever-smaller length scales.Unfortunately, there is today a growing consensus within industry, academia, and government labs that semiconductor scaling has not very much life left; maybe 10 years or so, at best. Multiple issues that come into play as we dive deeper into the nanoscale mean that the classic scaling trends are losing steam. Already, the decreasing logic voltages required due to various short-channel effects resulted in the plateauing of clock speeds more than a decade ago, driving the shift towards today's multi-core architectures. But now, even multi-core architectures face the looming threat of increasing amounts of "dark silicon," 5,6 as heat dissipation constraints prevent us from being able to cram any more operations per second into each unit of chip area, due to the energy that is converted to heat in each operation. Fundamentally, achieving higher performance within a system of any given size, cost, and power budget requires that individual

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A Mini-MIPS microprocessor for adiabatic computing

Cited by 11 publications

References 16 publications

Modelling, simulation and verification of 4-phase adiabatic logic design: A VHDL-Based approach

Modelling, simulation and verification of 4-phase adiabatic logic design: A VHDL-Based approach

Challenges to adopting adiabatic circuits for systems‐on‐a‐chip

Back to the Future: The Case for Reversible Computing

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