Abstract:This paper studies how high-performance computer servers, equipped with Field-Programmable Gate Arrays (FPGAs), can perform high-speed routing. In particular, routing table lookup is considered since it is a key packet processing bottleneck for future routers that need to operate at Petabits-per-second.The paper defines and evaluates three routing lookup schemes used by routers/switches, using Xilinx NetFPGA SUME programmable data plane hardware boards. Two existing schemes, namely IP address-based Longest Pre… Show more
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