A minimalist cache coherent MPSoC designed for FPGAs

Jr, Jorge Tortato; Hexsel, Roberto A.

doi:10.1504/ijhpsa.2011.040460

Cited by 1 publication

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“…It might be worth investigating novel implementations that could reduce the size of the FP logic, for example (i) reusing FP units to also do integer calculations, (ii) combining them as in [131], or (iii) sharing them between the CPU cores as done in RAMP Blue [81]. Furthermore, few works have addressed implementing cache coherent multiprocessors on FPGAs, some examples exist for MIPS [74] and PowerPC systems [78].…”

Section: Design Name Descriptionmentioning

confidence: 99%

A multicore emulator with a profiling infrastructure for transactional memory on FPGA

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This thesis attempts to bring together two recent topics by presenting a flexible Transactional Memory environment on a multicore prototype that is realized on FPGA fabric. For this, we devise a MIPS-compatible shared-memory multicore emulator with Hybrid Transactional Memory support, based on the Plasma open source soft processor core. We present the design and implementation of the TMbox system, which features an emulation system of up to 16 soft processor cores interconnected with a bi-directional ring bus, running at 50 MHz on a Virtex5-155t FPGA. Additionally, we build the first comprehensive infrastructure to profile Hybrid TM systems, an extensive visualization environment that enables examining complete transactional executions in detail. TMbox is a completely modifiable architecture implementing a multicore prototype with support for STM, HTM and Hybrid TM. It was written in various common design languages, and enables modifying the complete stack, down from the ISA, through the software toolchain, up to the well-optimized parallel code. With such an infrastructure, fast execution and quick performance evaluation can be made possible for studies in computer architecture. En esta tesis se propone juntar dos temas recientes a través de la creación de un sistema de memoria transaccional en un circuito programable (un FPGA). Para ello, ha sido diseñado un emulador de multinúcleo, con soporte para memoria transaccional híbrida y núcleos MIPS basados en el procesador de código libre Plasma. Presentamos el diseño y la implementación del sistema TMbox, que implementa un sistema de emulación de hasta 16 núcleos MIPS interconectados con un bus en anillo bidireccional, funcionando a 50 MHz en un FPGA Virtex5-155t. Adicionalmente, hemos construido la primera infraestructura para perfilado y visualización de memoria transaccional híbrida, que permite ver con un alto detalle ejecuciones transaccionales completas. TMbox es una arquitectura completamente modificable, e implementa un prototipo de un multinúcleo con memoria transaccional en software, hardware e híbrido. Está compuesto de varios lenguajes de diseño muy comunes, y habilita modificar el stack completo, desde la ISA, pasando por el toolchain de software, hasta el código paralelo altamente optimizado. Con una infraestructura como TMbox, es posible la ejecución veloz y la evaluación rápida del rendimiento en investigaciones de arquitectura de computadores.

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Section: Design Name Descriptionmentioning

confidence: 99%

A multicore emulator with a profiling infrastructure for transactional memory on FPGA

Sönmez

View full text Add to dashboard Cite

show abstract

A minimalist cache coherent MPSoC designed for FPGAs

Cited by 1 publication

References 20 publications

A multicore emulator with a profiling infrastructure for transactional memory on FPGA

A multicore emulator with a profiling infrastructure for transactional memory on FPGA

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