A mixed sample-time error calibration technique in time-interleaved ADCs

Abstract

Sample-time error between channels degrades resolution of time-interleaved analog-to-digital converters (TIADCs). A calibration method implemented in mixed circuits with low-complexity and fast-convergence is proposed in this paper. The algorithm for detecting sample-time error, which is widely applied to wide-sense stationary input signals, is based on correlation. The detected sample-time error is corrected by a voltage-controlled sampling switch. Experimental result of a 2-channel 200-MS/s 14-bit TIADC shows that the signal-to-noise-and-distortion ratio improves 19.1 dB, and the spurious-free dynamic range improves 34.6 dB for a 70.12-MHz input after calibration. The convergence time of the calibration is about 20000 sampling intervals.

Novel sifting-based solution for multiple-converter synchronization of ultra-fast TIADC systems

“…Associated with the timing in Fig. 2, it can be found that the measuring accuracy can be expanded effectively by the corresponding delay t d i on each DCLK i except DCLK 1 . But the range of such delays shall fall within a T DCLK , and every time interval shall be measurable and separable strictly, i.e.,…”

“…For breaking through the limitations of analog-todigital converter (ADC) performance and acquiring waveform information of measured signals with higher sampling rate, parallelism based time-interleaved ADC (TIADC) technology has been widely adopted as a very effective and practicable method by improving real-time sampling frequency. In recent years, thanks to the development and perfection of mismatch calibration method of offset, gain, time and frequency-response, this technology has nearly solved the performance inconsistency among multiple converters and improved the overall sampling performance of the system to that of single ADC [1,2,3,4]. With the further increase of sampling frequency, however, synchronous reset operations among multiple converters may cause the random nondeterminacy of phase differences among multiple data synchronous clocks (DCLKs).…”

A channel multiplexing digital calibration technique for timing mismatch of time-interleaved ADCs

“…Timing mismatch in TIADC can be calibrated through analog or mixed-signal techniques [5,6,7,8,9], but the calibration precision in analog domain is limited by the process. The all-digital calibration technique, by contrast, seems to be a more promising and robust solution under various processes [10].…”

Calibration technique for new-structure, two-channel hybrid filter banks ADC

“…TIADC is extremely sensitive to the time skew, which make it not suitable for high-resolution, and the condition will be worse as the number of channels increasing. Although there are many algorithms proposed to calibration these mismatches, the results after calibration are still not satisfactory [1,2,3,4].…”