A mixed signal rotator/shifter for 8GHz Intel/spl reg/ Pentium/spl reg/ 4 integer core

Singh, A.P.; Barany, Micah; Deleganes, D.J.

doi:10.1109/vlsic.2004.1346627

Cited by 4 publications

(2 citation statements)

References 2 publications

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“…Vector shifts/rotates and permute are key functions for maximizing vector data-path utilization in SIMD applications and are power and performance critical components of this specialized SIMD hardware [4,5]. SIMD arithmetic computations for multiple bit-width operands require parallel discrete-width shifters resulting in power and area overheads.…”

Section: Introductionmentioning

confidence: 99%

A 260mV 468GOPS/W 256b 4-way to 32-way vector shifter with permute-assisted skip in 22nm tri-gate CMOS

Agarwal

Hsu

Mathew

et al. 2012

2012 Proceedings of the ESSCIRC (ESSCIRC)

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A 4-way to 32-way reconfigurable 256b vector shifter with measured 2.3GHz operation consuming 41mW is fabricated in 0.9V, 22nm tri-gate CMOS. Byte-wise any-to-any permute-assisted skip for coarse-grained byte shifts, rotateback shifter, reconfigurable mask bit generation/decoder and ultra-low voltage circuits enable 38% area reduction and 240mV-1.1V wide dynamic voltage range with a measured 8.2x higher energy efficiency at 260mV compared to nominal 0.9V operation.

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Section: Introductionmentioning

confidence: 99%

A 260mV 468GOPS/W 256b 4-way to 32-way vector shifter with permute-assisted skip in 22nm tri-gate CMOS

Agarwal

Hsu

Mathew

et al. 2012

2012 Proceedings of the ESSCIRC (ESSCIRC)

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“…A 4-bit barrel shifter in the QCA computing paradigm was introduced in [11]. A mixed signal 32-bit rotator/shifter circuit design with short latency was discussed in [12]. Several low-power architectures for barrel shifters have been presented in [13]- [15] and [16].…”

Section: Introductionmentioning

confidence: 99%

A Timing-Driven Approach to Synthesize Fast Barrel Shifters

Das¹,

Khatri

2008

IEEE Trans. Circuits Syst. II

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In modern digital signal processing and graphics applications, the shifter is an important module, consuming a significant amount of delay. This brief presents an architectural optimization approach to synthesize a faster barrel shifter block, which can be useful to reduce the delay of the design without significantly increasing the area. We have divided the problem of generating the shifter into two steps: i) timing-driven selection of multiple stages for merging, and ii) the design of the merged stage. In our proposed method, we define the notion of dual merged stage, where two stages are merged and the triple merged stage, where three stages are merged into a single composite stage. These merged stages are identified by using a timing-driven algorithm and are used in conjunction with some single stages of the traditional barrel shifter. The use of these merged stages helps reduce the depth of the proposed barrel shifter architecture, thereby improving the delay. The timing-driven nature of our algorithm helps produce a faster implementation for the overall shifter block. We have evaluated the performance of our design by using a number of technology libraries, timing constraints and shifter bit-widths. Our experimental data shows that the shifter block generated by our algorithm is significantly faster (10.19% on average) than the shifter block generated by a commercially available datapath synthesis tool. These improvements were verified on placed-and-routed designs as well.

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Low-voltage swing logic circuits for a Pentium/spl reg/ 4 processor integer core

Deleganes

Barany

Geannopoulos

et al. 2005

IEEE J. Solid-State Circuits

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A mixed signal rotator/shifter for 8GHz Intel/spl reg/ Pentium/spl reg/ 4 integer core

Cited by 4 publications

References 2 publications

A 260mV 468GOPS/W 256b 4-way to 32-way vector shifter with permute-assisted skip in 22nm tri-gate CMOS

A 260mV 468GOPS/W 256b 4-way to 32-way vector shifter with permute-assisted skip in 22nm tri-gate CMOS

A Timing-Driven Approach to Synthesize Fast Barrel Shifters

Low-voltage swing logic circuits for a Pentium/spl reg/ 4 processor integer core

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