2019
DOI: 10.1007/s10617-019-09229-y
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A model-driven framework for design and verification of embedded systems through SystemVerilog

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Cited by 49 publications
(13 citation statements)
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“…Transformation rules are the set of formal definitions [34] that define how one or more constructs in source model language map to one or more constructs in target model language [18]. While developing transformation rules, main focus is to reduce overall efforts and information loses during transformation process [17].…”
Section: B Transformation Rulesmentioning
confidence: 99%
“…Transformation rules are the set of formal definitions [34] that define how one or more constructs in source model language map to one or more constructs in target model language [18]. While developing transformation rules, main focus is to reduce overall efforts and information loses during transformation process [17].…”
Section: B Transformation Rulesmentioning
confidence: 99%
“…A special mention should be done on Assertion Based Verification techniques, which include formal verification methods where designs are verified against certain assertions. In [15] a unified framework for executing static and dynamic verification [16] for embedded systems design is presented. One common static verification method is Timed Automata Models [17] which allow determining whether or not temporal requirements are met.…”
Section: A Related Workmentioning
confidence: 99%
“…The work in this article is significant to the existing body of research knowledge in two different ways: (a) From an application developer's perspective, the proposed work provides two major benefits: simplicity and reusability [21,22]. The simplicity is achieved by providing a model-based solution at higher abstraction level.…”
Section: Plos Onementioning
confidence: 99%