A Model-Driven Platform for Dynamic Partially Reconfigurable Architectures: A Case Study of a Watermarking System

Abstract

The reconfigurable feature of FPGAs (Field-Programmable Gate Arrays) has made them a very attractive solution for implementing adaptive systems-on-chip. However, this implies additional design tasks to handle system reconfiguration and control, which increases design complexity. To address this issue, this paper proposes a model-driven design flow that guides the designer through the description of the different elements of a reconfigurable system. It is based on high-level modeling using an extended version of the MARTE (Modeling and Analysis of Real-Time and Embedded systems) UML (Unified Modeling Language) profile. Both centralized and decentralized reconfiguration decision-making solutions are possible with the proposed flow, allowing it to adapt to various reconfigurable systems constraints. It also integrates the IP-XACT standard (standard for the description of electronic Intellectual Properties), allowing the designer to easily target different technologies and commercial FPGAs by reusing both high-level models and actual IP-XACT hardware components. At the end of the flow, the implementation code is generated automatically from the high-level models. The proposed design flow was validated through a reconfigurable video watermarking application as a case study. Experimental results showed that the generated system allowed a good trade-off between resource usage, power consumption, execution time, and image quality compared to static implementations. This hardware efficiency was achieved in a very short time thanks to the design acceleration and automation offered by model-driven engineering.

Editorial for the Special Issue on Network on Chip (NoC) and Reconfigurable Systems

“…In this Special Issue on Network on Chip (NoC) and Reconfigurable Systems, we include eight papers covering different aspects related to 3D NoC [ 1 , 2 ], GALS NoC [ 3 ], NoC routing [ 4 , 5 , 6 ], application of NoC to the Internet of Things (IoT) [ 7 ], and dynamic partially reconfigurable architectures [ 8 ].…”

“…A sophisticated proportional–integral–derivative (PID) controller and a quasi-sliding mode controller (QSMC) have been designed to synchronize the master-slave chaotic systems for decrypting the signals. Finally, in [ 8 ], Dalbouchi et al study the reconfigurable feature of FPGAs (Field-Programmable Gate Arrays) that made them a desirable solution for implementing adaptive SoC by proposing a model-driven design flow that guides the designer through the description of the different elements of a reconfigurable system. The proposed model is based on high-level modeling using an extended version of the MARTE (Modeling and Analysis of Real-Time and Embedded Systems) UML (Unified Modeling Language) profile.…”