A model for the field and temperature dependence of Shockley-Read-Hall lifetimes in silicon

Schenk, Andreas

doi:10.1016/0038-1101(92)90184-e

Cited by 308 publications

(133 citation statements)

References 38 publications

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“…In order to describe band-to-band tunneling (BTBT) mechanism in forward bias of tunnel diode, our numerical BTBT model has been incorporated [11]. For the leakage current behaviors through a forbidden energy band-gap, conventional fielddependent TAT model is used [12]. Basic operation principle of our NDR device with ultra-high PVCR is that NW transistor can completely suppress the valley current creating NDR region.…”

Section: Device Operation Principle and Multiple Ndrsmentioning

confidence: 99%

Negative Differential Resistance Devices with Ultra-High Peak-to-Valley Current Ratio and Its Multiple Switching Characteristics

Shin¹,

Kang²,

Kim³

2013

JSTS:Journal of Semiconductor Technology and Science

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Abstract-We propose a novel negative differential resistance (NDR) device with ultra-high peak-tovalley current ratio (PVCR) by combining pn junction diode with depletion mode nanowire (NW) transistor, which suppress the valley current with transistor off-leakage level. Band-to-band tunneling (BTBT) Esaki diode with degenerately doped pn junction can provide multiple switching behavior having multi-peak and valley currents. These multiple NDR characteristics can be controlled by doping concentration of tunnel diode and threshold voltage of NW transistor. By designing our NDR device, PVCR can be over 10 4 at low operation voltage of 0.5 V in a single peak and valley current.

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Section: Device Operation Principle and Multiple Ndrsmentioning

confidence: 99%

Negative Differential Resistance Devices with Ultra-High Peak-to-Valley Current Ratio and Its Multiple Switching Characteristics

Shin¹,

Kang²,

Kim³

2013

JSTS:Journal of Semiconductor Technology and Science

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“…Simulation works on CMOS latchup immunity [4], memory cell alpha-particle induced soft error [ 5 ] , Si crystal defects formation due to LOCOS process related mechanical stress [6] and electric-field enhanced SRH recombination [7] have been conducted.…”

Section: Analysis Of Critical Phenomenamentioning

confidence: 99%

Applied TCAD in Mega-Bits Memory Design

Masuda

Pimingstorfer

Sato

et al. 1993

Simulation of Semiconductor Devices and Processes

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This paper describes a methodology of TCAD application in VLSI design and development. Simulation-based circuit model parameter generation for chip design purpose is one of the key topics in TCAD. Several critical phenomena, such as CMOS latchup etc., were also analyzed to verify feasibility and performance of the memory process. Two months of TCAD analysis were required, in which twelve sets of MOS model parameters were generated by VISTA with the computational cost of six hours on six CPUs of SGI-IRIS machines. Basic Data for TCAD DesignFor submicron devices, the shallow junction formation is one of the essential processes which determine the device performance. To verify the impurity profile of ion-implanted and annealed diffusion layer, we used SIMS measurement for B, P, and As impurities. Over a hundred samples with various doping conditions have been analyzed. Enhanced diffusion model parameters with annealing temperature and dose have been extracted. Figure 1 shows an example of a Phosphorous implantation/diffusion profile which exhibits dose dependent TED (Transient Enhanced Diffusion) phenomena [I]. The two-dimensional profile of the Phosphorous diffusion was also verified as shown in Fig. 2 [2]. The result shows an isotropic nature of TED for Phosphorous. In circuit design, threshold control and driving current of the device are two major characteristics which determine chip performance and yield. We found an anomalous degradation of submicron MOS driving current based on a study of intrinsic drain current, as shown in Fig. 3 [3]. A simple model which describes carrier-velocity-saturation has been developed to clarify the phenomena. Experimental Id, -L curves in submicron NMOS and the proposed model allow us prediction of effective drain current of submicron NMOS as shown in Fig. 4. Analysis of Critical PhenomenaIn CMOS memory process, a couple of critical phenomena have to be evaluated. Simulation works on CMOS latchup immunity [4], memory cell alpha-particle induced soft error [ 5 ] , Si crystal defects formation due to LOCOS process related mechanical stress [6] and electric-field enhanced SRH recombination [7] have been conducted.

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“…The doping dependent mobility model 6) and high field saturation model 7) were used as mobility models. The impact ionization model 8) , band-to-band tunneling model 9) and SRH Recombination model 10) were used as generation and recombination models.…”

Section: Methodsmentioning

confidence: 99%

Effects of Source and Drain Impurity Profile on Breakdown Voltage of High-Performance Si TFTs

Tsuboi¹,

Kawachi²,

Mitani³

et al. 2007

Eizo Joho Media Gakkaishi

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A model for the field and temperature dependence of Shockley-Read-Hall lifetimes in silicon

Cited by 308 publications

References 38 publications

Negative Differential Resistance Devices with Ultra-High Peak-to-Valley Current Ratio and Its Multiple Switching Characteristics

Negative Differential Resistance Devices with Ultra-High Peak-to-Valley Current Ratio and Its Multiple Switching Characteristics

Applied TCAD in Mega-Bits Memory Design

Effects of Source and Drain Impurity Profile on Breakdown Voltage of High-Performance Si TFTs

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