A modified low voltage triggered silicon controlled rectifier (SCR) for ESD applications

Abstract

In this paper, a modified low voltage triggered silicon-controlled rectifier (MLVTSCR) with low trigger voltage and high holding voltage has been proposed and implemented in both 28 nm CMOS process and 0.18 μm CMOS process. By segmenting the N + active area bridged on the PW/NW junction of LVTSCR into blocks by P + region, MLSCR was integrated into LVTSCR. The p + blocks and the n + blocks are alternately arranged and aligned in the same strip, in this way the proposed MLVTSCR is implemented. Without any extra mask as well as auxiliary trigger component, the proposed MLVTSCR possesses a very low trigger voltage and an adjustable high holding voltage from 2.05 to 4.29 V in 28 nm CMOS process and from 3.32 to 7.3 V in 0.18 μm BCD process under the TLP test, making it a superior candidate for electrostatic discharge protection in the 3.3 V/5 V CMOS processes. TCAD simulations has also been carried out to explore the intrinsic physical mechanisms of the proposed devices.

Enhancement of holding voltage by a modified low-voltage trigger silicon-controlled rectifier structure for electrostatic discharge protection

“…This improved method will build an auxiliary current discharge path, which can increase the holding voltage. [17] However, this method will reduce the failure current value and affect the robustness of the device.…”