A modified macro model approach for SPICE based simulation of single electron transistor

Ghosh, Arpita; Jain, Amit; Singh, N. Basanta; Sarkar, Subir Kumar

doi:10.1007/s10825-015-0790-1

Cited by 18 publications

(5 citation statements)

References 31 publications

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“…There are three main methods for simulating single electron circuits: SPICE macro-modeling, Monte Carlo based, and Master Equation based, each with its own unique approach to the simulation process. SPICE, a faster singleelectron simulator, can model the IV characteristic of single-electron transistors, but lacks Coulomb interaction, which can be resolved with pre-processing steps [51], [52], [53].…”

Section: Ivsingle Electron Transistor Simon Simulationmentioning

confidence: 99%

Analytical Modelling and Performance Characterization of Single Electron Transistor

Shruti Suman

2024

jes

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One important component of the present nanotechnology research field is single electron transistor (SET) which has unrealized quality to operate at breakneck speeds with ultralow power consumption. The single electron transistor is a novel nanoscale switching device that can regulate the motion of a single electron in addition to maintaining its scalability down to the atomic level. In this context, scalability refers to the ability of electronic device to function better as their dimensions get smaller. The basic device properties that this single electron transistor (SET) operates on "quantized current-voltage (I-V) characteristic," "single electron tunneling effect," and "Coulomb blockade," are also covered. This study presents some of the key SET-related topics, such as modelling and simulation methods. Simulation of Nanostructures Method (SIMON) is circuit simulator for tunneling device with just a single electron device based on Monte Carlo approach. It enables simulation of any kind of circuits with voltage source, junctions in tunnels and capacitors in quasi stationary mode and transient mode. The most significant feature of SET that is applied in the research work is Coulomb blockade oscillation, so at the conclusion of this paper, a number of simulations utilizing the SIMON simulator are shown. The simulation results show that for gate capacitance CG = 2af, C∑ = 3af, IBIAS = 2nA, tunnel barrier resistance RT > 4.1KΩ and operating temperature T=21K the model reflects real SET characteristic with maximum voltage gain.

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Section: Ivsingle Electron Transistor Simon Simulationmentioning

confidence: 99%

Analytical Modelling and Performance Characterization of Single Electron Transistor

Shruti Suman

2024

jes

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“…There are three main approaches for simulating single-electron circuits, viz. the master equation-based approach [26], the Monte Carlo method [27], the and macro model-based approach [28,29].…”

Section: The Se-tlg-based Design Of the 2 × 2 Binary Multipliermentioning

confidence: 99%

The design and performance of different nanoelectronic binary multipliers

Ghosh¹,

Jain

Sarkar

2021

J Comput Electron

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The design and performance of digital binary multipliers built using different types of nanoelectronic devices are investigated herein. Designs for 2 × 2 binary multipliers implemented using different technologies such as single-electron-threshold logic (SE-TLG), hybrid single-electron transistor/complementary metal-oxide-semiconductor (SET-CMOS), and carbon nanotube field-effect transistor (CNFET) devices are elaborated and presented with corresponding simulation results. The performance metrics considered for their comparison are the power consumption, the circuit area, the propagation delay, the operating temperature, the design platform, etc. The existing CMOS-based design is also compared with all three proposed designs. The comparative analysis indicates that the SE-TLG-based 2 × 2 binary multiplier design exhibits very low power consumption, the smallest area requirement, and the shortest propagation delay among the three. Meanwhile, the design based on hybrid SET-CMOS devices can operate at room temperature and delivers the optimal response in terms of all the other performance metrics when compared with the other circuit implementations considered herein. Further stability analysis of the designs based on SE-TLG and hybrid SET-CMOS devices is carried out to validate their performance.

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“…Macromodeling is propitious for simplifying circuit structures and reducing simulation times, but the precision of such simulations may not be high enough and the internal states of the considered SET cannot be measured. The Monte Carlo method is used to calculate the probability of tunneling events that occur on Coulomb islands [17]. However, this method consumes too much time when performing probability calculations, which is highly undesirable in terms of the simulation process.…”

Section: Choosing the Simulation Platform And Set Modelmentioning

confidence: 99%

“…In this sense, single-electron transistors (SETs) have attracted attention from researchers due to their smaller space occupation, simpler structure, and lower energy consumption compared with traditional FETs [16]. The basic operational principles of a SET are Coulomb blockade oscillation and the tunneling effect, with only a few electrons being transported [17]. Based on these remarkable characteristics, many circuits have been designed [18,19].…”

Section: Introductionmentioning

confidence: 99%

Memristive-synapse spiking neural networks based on single-electron transistors

Long

Zhang

2019

J Comput Electron

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In recent decades, with the rapid development of artificial intelligence technologies and bionic engineering, the spiking neural network (SNN), inspired by biological neural systems, has become one of the most promising research topics, enjoying numerous applications in various fields. Due to its complex structure, the simplification of SNN circuits requires serious consideration, along with their power consumption and space occupation. In this regard, the use of SSN circuits based on single-electron transistors (SETs) and modified memristor synapses is proposed herein. A prominent feature of SETs is Coulomb oscillation, which has characteristics similar to the pulses produced by spiking neurons. Here, a novel window function is used in the memristor model to improve the linearity of the memristor and solve the boundary and terminal lock problems. In addition, we modify the memristor synapse to achieve better weight control. Finally, to test the SNN constructed with SETs and memristor synapses, an associative memory learning process, including memory construction, loss, reconstruction, and change, is implemented in the circuit using the PSPICE simulator.

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A modified macro model approach for SPICE based simulation of single electron transistor

Cited by 18 publications

References 31 publications

Analytical Modelling and Performance Characterization of Single Electron Transistor

Analytical Modelling and Performance Characterization of Single Electron Transistor

The design and performance of different nanoelectronic binary multipliers

Memristive-synapse spiking neural networks based on single-electron transistors

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