A modified NCO based LSPF-DPLL Phase Resolver for wireless communication

A Parallelized Phase-Frequency Detector based Modified LSPF-DPLL for Wireless Communication – Comparative Study with Modified LSPF-DPLL

“…Digital Phase Locked Loops (DPLLs) are the sampled domain extraction of the Phase Locked Loops (PLLs) realized by means of a digital Phase-Frequency Detector (PFD) [1,2]. Popularly referred to as an FM demodulator, DPLL plays diverse roles in communication systems which include recovering carrier information in noncoherent systems where the channel state is not known to the receiver [2], symbol retrieval in coherent links for known channel [3], multi-clock synchronization and clock distribution into different sub-systems using divider unit in PLLs besides time synchronizing such systems [2].…”

“…This system also shows excellent error performance but lacks time efficiency. An MPR-NCO based LSPF-DPLL system is proposed in [1] for wireless fading environments and emerges as an improved design over the existing LSPF-DPLL [2] with better error and time performance.…”

“…The recent trend in wireless communications as can be seen in [1,4] is time efficient symbol recovery. Certain DPLL designs however emphasize on significant reduction in BER levels and therefore involve intensive computations which lead to poor time performance [2,3].…”

“…The LSPF-DPLL in [2] additionally also involves another hugely time-intensive LSPF based PFD unit. An MPR-NCO based LSPF-DPLL has been recently proposed in [1] and exhibits improved error and time performance over the existing design in [2]. The time efficiency improvement in [1] is solely due to the incorporation of the MPR-NCO.…”

“…An MPR-NCO based LSPF-DPLL has been recently proposed in [1] and exhibits improved error and time performance over the existing design in [2]. The time efficiency improvement in [1] is solely due to the incorporation of the MPR-NCO. The design presented here tries to further improve system time performance by parallelizing the operations of intensive LSPF based PFD in [1] using the different cores of a Quad Core processor while maintaining the system's error performance.…”