A Modified Radix-16 CORDIC Algorithm-based Direct Digital Frequency Synthesizer

Changela, Ankur; Kumar, Yogesh

doi:10.1109/ic3i56241.2022.10072732

Cited by 1 publication

(1 citation statement)

References 13 publications

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“…Ref. [21] applied an improved radix-16 CORDIC algorithm to direct digital frequency synthesis, reducing iteration counts from N to N/2+2 and significantly decreasing system latency. Ref.…”

Section: Introductionmentioning

confidence: 99%

Design of Hardware IP for 128-Bit Low-Latency Arcsinh and Arccosh Functions

Chang,

Wang

2023

Electronics

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With the rapid development of technologies like artificial intelligence, high-performance computing chips are playing an increasingly vital role. The inverse hyperbolic sine and inverse hyperbolic cosine functions are of utmost importance in fields such as image blur and robot joint control. Therefore, there is an urgent need for research into high-precision, high-performance hardware Intellectual Property (IP) for arcsinh and arccosh functions. To address this issue, this paper introduces a novel 128-bit low-latency floating-point hardware IP for arcsinh and arccosh functions, employing an enhanced Coordinate Rotation Digital Computer (CORDIC) algorithm, achieving a computation precision of 113 bits in just 32 computation cycles. This significantly enhances computational efficiency while reducing hardware implementation latency. The results indicate that, when compared to Python standard results, the calculated error of the proposed hardware IP does not exceed 8×10−34. Furthermore, this paper synthesizes the completed IP using the TSMC 65 nm process, with a total IP area of 2.1056 mm2. Operating at a frequency of 300 MHz, its power is 22.4 mW. Finally, hardware implementation and resource analysis are conducted and compared on an Field Programmable Gate Array (FPGA). The results show that the improved algorithm trades a slight area increase for lower latency and higher accuracy. The designed hardware IP is expected to provide a more accurate and efficient computational tool for applications like image processing, thereby advancing technological development.

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“…Ref. [21] applied an improved radix-16 CORDIC algorithm to direct digital frequency synthesis, reducing iteration counts from N to N/2+2 and significantly decreasing system latency. Ref.…”

Section: Introductionmentioning

confidence: 99%

Design of Hardware IP for 128-Bit Low-Latency Arcsinh and Arccosh Functions

Chang,

Wang

2023

Electronics

View full text Add to dashboard Cite

show abstract

A Modified Radix-16 CORDIC Algorithm-based Direct Digital Frequency Synthesizer

Cited by 1 publication

References 13 publications

Design of Hardware IP for 128-Bit Low-Latency Arcsinh and Arccosh Functions

Design of Hardware IP for 128-Bit Low-Latency Arcsinh and Arccosh Functions

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