A Modified SOGI-PLL with Adjustable Refiltering for Improved Stability and Reduced Response Time

Herrejon-Pintor, G.A.; Melgoza-Vázquez, Enrique; Chávez, Jose de Jesús

doi:10.3390/en15124253

Cited by 11 publications

(9 citation statements)

References 32 publications

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“…For simplicity, the filter structure of two-level SOGI modules cascading as shown in Figure 6b is analyzed. When phase locking is successful and stable, the following formula can be obtained: After some mathematical manipulation, it can be derived by substituting (13) into (15).…”

Section: System Modellingmentioning

confidence: 99%

“…Although this method will not affect the bandwidth of the PLL, a phase compensation unit and a frequency adaptation link must be added to ensure normal operation. The second type of method is to add a filter within the PLL, such as SOGI module [12][13][14][15]. SOGI-PLL has two mutually coupled feedback loops: one feeds the estimated phase angle back to the Park transform, while the other feeds the estimated angular frequency back to the SOGI.…”

Section: Introductionmentioning

confidence: 99%

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Analysis and modelling of a phase‐locked loop based on a novel cascade structure of SOGI

Ke,

2023

IET Power Electronics

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In order to attenuate the oscillations on the estimated frequency of a phase‐locked loop (PLL), the effective suppression of low‐order harmonics in grid voltage is a crucial issue in three‐phase grid‐connected inverters, which use the standard PLL based on a double second‐order generalized integrator (DSOGI‐PLL). Analysis shows that the SOGI module exerts a stronger filtering effect in generating the quadrature signal than the in‐phase signal. In this context, two novel cascaded SOGI module filtering structures have been developed, based on which the PLLs are proposed. In comparison to the previously proposed method for addressing the problem of input voltage harmonics, the proposed method has stronger filtering ability and can flexibly select the levels of SOGI module cascading based on the degree of grid voltage distortion to achieve a balance between system dynamic performance and filtering performance. The proposed PLLs' approximation small signal model is established, and the method for designing the system control parameters is also provided. In the case of frequency steps, phase angle jumps, harmonic injection, and unbalanced voltage sag, Matlab modelling and experimental results demonstrate that the proposed PLLs can efficiently extract the frequency and phase of the fundamental positive sequence component and behave better in steady‐state and dynamic performance.

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Section: System Modellingmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Analysis and modelling of a phase‐locked loop based on a novel cascade structure of SOGI

Ke,

2023

IET Power Electronics

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“…The power generated from RESs must be shaped in order to be interfaced with the grid by employing Power Electronics Converters (PEC) [3]. In grid-connected RES systems, the most popular synchronization technique is based on Phase-Locked Loops, (PLL) which synchronize the output power from the PEC with the electrical grid [4][5][6][7][8].…”

Section: Introductionmentioning

confidence: 99%

Grid-Connected Renewable Energy Sources: A New Approach for Phase-Locked Loop with DC-Offset Removal

Bany Issa,

Al Muala,

Bello Bugallo

2023

Sustainability

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Renewable Energy Sources (RES) are widely used worldwide due to their positive effect on the environment, being sustainable, low cost, and controllable. The power generated from RESs must be configured to interface and perfectly synchronize with the grid by using Power Electronics Converters (PEC). A Phase-Locked Loop (PLL) is one of the most popular synchronization techniques used due to its speed and robustness. A growing issue that results in oscillations in the estimated fundamental grid phase, frequency, and voltage amplitude is the DC-offset in the input of the PLL. This study was developed to eliminate the DC-offset in the single-phase grid synchronization using Delay Signal Cancellation (DSC) and a fixed-length Transfer Delay (TD)-based PLL. Then, the small-signal model, stability analysis, and selection of controller gains were discussed. The proposed PLL was simulated using MATLAB/Simulink. Moreover, to evaluate the proposed method, several scenarios were developed in order to compare it with other powerful PLLs in terms of performance indicators such as settling time, frequency, and phase error. As a result, the proposed PLL has the fastest dynamic response, completely rejects the DC-offset effect, and fully synchronizes with the electrical grid.

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“…Compared with open-loop algorithms, closed-loop algorithms have stronger antidisturbance abilities, among which, a PLL is most commonly used for its high precision and strong anti-disturbance ability. A PLL consists of a phase detector (PD), a loop filter (LF), and a voltage-controlled oscillator (VCO) [17]. In [18], considering an unknown load torque and friction effects, a PLL is used to estimate the angle position, and a robust position backstepping tracking controller is designed to ensure the trajectory-tracking performance of the motor.…”

Section: Introductionmentioning

confidence: 99%

Suppressing Quadrature Error and Harmonics in Resolver Signals via Disturbance-Compensated PLL

Wang

2022

Machines

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The aim of this study was to obtain accurate angular positions and velocities from resolver signals; resolver-to-digital conversion (RDC) often adopts a phase-locked loop (PLL) as a demodulation algorithm. However, resolver signals often come with quadrature errors and harmonics, which lead to a severe reduction in PLL accuracy. The conventional PLL does not consider the impact of the quadrature error, and the bandwidth of the PLL is much larger than the fundamental frequency of resolver signals for pursuing a low dynamic error. These reasons render the retention of resolver harmonics in the demodulation results. In this paper, a disturbance-compensated PLL (DC-PLL) is proposed, which consists of a phase detector for suppressing quadrature error and harmonics (SQEH-PD) and a second-order observer. Firstly, since the quadrature error does not change with the angle velocity, the pre-estimated quadrature error is used in the SQEH-PD to compensate for the quadrature error in resolver signals. Secondly, although the frequency of the harmonics changes with the velocity, the amplitudes of the harmonics do not change. Therefore, the pre-estimated amplitudes of harmonics and estimated angular position are used in the SQEH-PD to compensate for the harmonics in resolver signals. Thirdly, a second-order observer is designed to estimate the angular position and velocity by regulating the phase detector error. Compared with the conventional PLL, the proposed DC-PLL has a stronger anti-disturbance ability against the quadrature error and harmonics by configurating the phase detector error and the estimated position error, which have a linear relation. Simulation and experimental results prove the effectiveness of the proposed method.

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A Modified SOGI-PLL with Adjustable Refiltering for Improved Stability and Reduced Response Time

Cited by 11 publications

References 32 publications

Analysis and modelling of a phase‐locked loop based on a novel cascade structure of SOGI

Analysis and modelling of a phase‐locked loop based on a novel cascade structure of SOGI

Grid-Connected Renewable Energy Sources: A New Approach for Phase-Locked Loop with DC-Offset Removal

Suppressing Quadrature Error and Harmonics in Resolver Signals via Disturbance-Compensated PLL

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