A Modified Topology Of Asymmetrical 9-Levels Cascaded Multilevel Inverter

Ghamudi, Mohaned Nser A; Abdulhamed, Zeyad E.; Esuri, Abdulhamid H.

doi:10.1109/mi-sta52233.2021.9464358

Cited by 4 publications

(1 citation statement)

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“…The design can be divided into two sections as shown in Figure 2. The first section consists of SW1-6, and it is a modified version of a design proposed by [15], this circuit can generate four voltage levels, namely: VA, VB, VA+VB, VA−VB. The second section is a modified diode clamped inverter introduced in [12], which can divide the voltage by a factor of two, so the output of this section will be the voltage levels from section one divided by two: VA/2, VB/2, (VA+VB)/2, (VA−VB)/2.…”

Section: Circuit Descriptionmentioning

confidence: 99%

17 Level Hybrid Diode Clamped Inverter With Reduced Number of Components

Alsumady,

Jaber,

Nusserat

2023

J. Electron. Electric. Eng.

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Multilevel inverters (MLIs) are gaining more interest recently in medium to high power applications. The main problem with various MLI topologies is that they require a large number of switching devices and DC voltage sources while producing a small number of voltage levels. Which results in bulky inverters with high cost and high output voltage/current total harmonic distortion (THD). This paper introduces a new novel asymmetrical 17-level MLI design using two DC voltage sources and a reduced number of switches. This was achieved by combining a voltage summing and subtracting circuit with a modified diode clamped MLI (DC-MLI), which divides the voltage by two. Thus, generating more voltage levels. nearest level control (NLC) is used to produce the switching signals at a switching frequency of 50Hz. The design is tested and simulated using MATLAB/Simulink, the output voltage THD is kept around 5.7%. The obtained results are compared with other recent 17-level topologies, showing that a good improvement is achieved.

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Section: Circuit Descriptionmentioning

confidence: 99%