A modular simulation framework for architectural exploration of on-chip interconnection networks

Abstract

Ever increasing complexity and heterogeneity of SoC platforms require diversified on-chip communication schemes beyond the currently omnipresent shared bus architectures. To prevent time consuming design changes late in the design flow, we propose the early exploration of the on-chip communication architecture to meet performance and cost requirements. Based on SystemC 2.0.1 we have defined a modular exploration framework, which is able to capture the effect on performance for different on-chip networks like dedicated point-to-point, shared bus, and crossbar topologies. Monitoring of performance parameters like utilization, latency and throughput drives the mapping of the inter-module traffic to an efficient communication architecture. The effectiveness of our approach is demonstrated by the exemplary design of a high performance Network Processing Unit (NPU), which is compared against a commercial NPU device.

On Mixed Abstraction, Languages, and Simulation Approach to Refinement with SystemC AMS

“…Among the less formal methods, a holistic way of interconnecting modules [9] uses UML SysML. Interface-based [10] partitioning of networked architecture is suited for NoC applications. Automatic IP selection was proposed by [11].…”

The routability of multiprocessor network topologies in FPGAs

“…Most NoC work assumes ASIC implementations and there are numerous studies including work on mesh topologies [6][9] and fat trees [7]. Other studies on NoCs are done using registertransfer-level simulations [7] and simulation models [11], but they do not show the implementation side of the NoC. Instead, we focus on the interaction between the network topologies and how well they can be mapped to a fixed FPGA routing fabric.…”