A monitoring system for NoCs

Abstract

In this paper, we propose and discuss a monitoring architecture for Networks-on-Chip (NoCs) that provides system information useful for helping designers in efficiently exploiting resources available in new complex Multiprocessor Systemon-Chip (MPSoC) platforms, and in understanding their behavior. We focus on the analysis of the architectural details and design challenges of such systems, by describing powerful tools for detecting information that can be used both at run-time for detecting dynamic changes in system behavior and at post-execution time for debugging and profiling of applications. We detail the design of the probes monitoring the events and discuss an architecture for collection, storage, and analysis of information generated by them. We evaluate cost of the implementation of the system in terms of area and traffic overhead, and we present results obtained when monitoring a use-case multimedia application. 1

Bus-based MPSoC Security through Communication Protection: A Latency-efficient Alternative

“…Xilinx Microblaze processor was taken as a reference for Table VII, individual configurations are indicated between brackets (caches size and clock frequency). In Table VII, our solution has a ratio lower than the Data Protection Unit system [5]: this may be due to the CAM system which is more complex than a Block RAM. SECA-based solution has a lower impact because the kernel (containing security configurations) is not included in this estimation while security policies stored in firewall BRAMs are taken into account in this analysis.…”

“…A management unit gathers all information from network interfaces according to a userdefined security policy. Fiorin et al [5] propose an alternative to this work by adding probes within the interface structure to refine the protection mechanisms. Each security-enhanced interface, considered as a trusted component, is composed by a set of probes, protection units and a kernel providing network management services.…”

“…The area results for our work does not take into account the Cryptographic Module because Coburn [6] and Fiorin [5] do not have ciphering features in their solutions. Xilinx Microblaze processor was taken as a reference for Table VII, individual configurations are indicated between brackets (caches size and clock frequency).…”

Lightweight reconfiguration security services for AXI-based MPSoCs

“…A management unit gathers all information from network interfaces according to a security policy. Fiorin et al [4][5] [6] propose an alternative to this work by adding probes within the interface structure to refine the protection mechanisms. These probes can block incoming traffic according to parameters stored in an embedded memory.…”

“…It is inspired by [6] with an implementation specific to the AXI bus standard with a low area/latency trade-off. Moreover, several scenarios and a case study are discussed to demonstrate all the features provided in this work.…”