A Monotonic Early Output Asynchronous Full Adder

Abstract

This article introduces a novel asynchronous full adder that operates in an input–output mode (IOM), displaying both monotonicity and an early output characteristic. In a monotonic asynchronous circuit, the intermediate and primary outputs exhibit similar signal transitions as the primary inputs during data and spacer application. The proposed asynchronous full adder ensures monotonicity for processing data and spacer, utilizing dual-rail encoding for inputs and outputs, and corresponds to return-to-zero (RtZ) and return-to-one (RtO) handshaking. The early output feature of the proposed full adder allows the production of sum and carry outputs based on the adder inputs regardless of the carry input when the spacer is supplied. When utilized in a ripple carry adder (RCA) architecture, the proposed full adder achieves significant reductions in design metrics, such as cycle time, area, and power, compared to existing IOM asynchronous full adders. For a 32-bit RCA implementation using a 28 nm CMOS technology, the proposed full adder outperforms an existing state-of-the-art high-speed asynchronous full adder by reducing the cycle time by 10.4% and the area by 15.8% for RtZ handshaking and reduces the cycle time by 9.8% and the area by 15.8% for RtO handshaking without incurring any power penalty. Further, in terms of the power-cycle time product, which serves as a representative measure of energy, the proposed full adder yields an 11.8% reduction for RtZ handshaking and an 11.2% reduction for RtO handshaking.

Monotonic Asynchronous Two-Bit Full Adder

“…The forward latency and reverse latency of RCAs comprising different OFAs have already been (approximately) modeled theoretically in [38]-an interested reader may refer to the same for details, as it is not repeated here. To specifically comment on the reduced cycle time achieved by the RCA incorporating the proposed TFA compared to RCAs incorporating other TFAs, we provide theoretical modeling of their forward and reverse latencies concerning R0H for an N-bit addition.…”

“…Thus, the cycle time of these relative-timed RCAs is given by O[(N + 1) × D OFA ], representing a theoretically optimal speed performance. Recently, a monotonic OFA was presented in [38] which when replicated to realize an IOM asynchronous RCA has a forward latency of O[N × D OFA ] and an optimal reverse latency of O[D OFA ], thus enabling a theoretically optimal cycle time of O[(N + 1) × D OFA ]. Compared to [29][30][31][32][33][34][35][36][37], ref.…”

“…Compared to [29][30][31][32][33][34][35][36][37], ref. [38] demonstrated reductions in all the standard design parameters such as area, cycle time, and power dissipation for both R0H and R1H.…”