A More Efficient and Flexible DSP Design Flow from Matlab-Simulink

Abstract

The design of complex Digital Signal Processing systems implies to minimize architectural cost and to maximize timing performances while taking into account communication and memory accesses constraints for the integration of dedicated hardware accelerator. Unfortunately, the traditional Matlab/ Simulink design flows gather not very flexible hardware blocs. In this paper, we present a methodology and a tool that permit the High-Level Synthesis of DSP applications, under both I/O timing and memory constraints. Based on formal models and a generic architecture, this tool helps the designer in finding a reasonable trade-off between the circuit's latency and its architectural complexity. The efficiency of our approach is demonstrated on the case study of a FFT algorithm.

A MATLAB GUI teaching application for ferroresonance simulation

“…It can be seen from the waveform diagram on the right that after the 0.2 s fault recovery, the system will be impacted and the fundamental frequency resonance will be triggered, which is characterized by the decrease of phase A voltage and the increase of phase B and C voltage, the system neutral point voltage increases, and the "illusory grounding" state. The frequency remains at the fundamental frequency during the resonance period [12,37].…”