A MOS-Based Temperature Sensor With Inherent Inaccuracy Reduction Enabled by Time-Domain Operation

Abstract

This article presents a MOS-based ON-chip temperature sensor system addressing both high-resolution and lowinaccuracy requirement, red while requiring a single temperature calibration point. Hence, the proposed temperature sensor system proves to be a low-cost solution, well addressing the requirements of the spreading market of system-on-chips (SoCs), mobile and wearable devices, and consumer electronics in general. The temperature sensor features a two-phase time-domain architecture, which employs as a sensing element a single NMOS transistor, biased alternatively with different currents, thus allowing achieving an inherent inaccuracy reduction. The proposed sensory system, fabricated in a standard 130-nm CMOS process, comprises, along the sensor core, a switched-capacitor analog interface circuit and a 1-bit second-order sigma-delta ( ) analog-to-digital converter (ADC). The proposed temperatureto-digital converter (TDC), experimentally characterized considering a batch of 16 samples, achieves 40-mK resolution at 20-kHz switching frequency and +0.75/−0.92 • C inaccuracy across the −40 • C-90 • C temperature range after one-point calibration at room temperature, consuming 25.4 µW, including the analog buffer added for testing purposes.

A 10.5 ppm/°C Modified Sub-1 V Bandgap in 28 nm CMOS Technology with Only Two Operating Points

“…This was reduced by choosing a higher n so that there is less of the multiplication factor, but the trade-off with a very high n increases the risk of the reverse saturation current. Figure 8 shows a simulated histogram of the output voltages corresponding to 6-Sigma 200 Monte Carlo simulations [24], indicating a standard deviation of 1.98 mV and an accuracy of 1.21%. Note each point in the histogram is a single Monte Carlo simulation.…”

Reference Temperature Sensor for TMOS-Based Thermal Detectors

“…With respect to [16], both the amplification and the analog-todigital conversion are performed by the ADC block, without employing an additional amplifier to provide gain before the ADC.…”

“…Reference voltages, V ref ,P and V ref ,N , as well as V S , are provided through analog buffers. The integrators, whose feedback networks implement 0.5 coefficients, are realized by amplifiers featuring a standard mirrored architecture [16]. A latched comparator, whose architecture is reported in [16], implements the single-bit quantizer.…”

“…The integrators, whose feedback networks implement 0.5 coefficients, are realized by amplifiers featuring a standard mirrored architecture [16]. A latched comparator, whose architecture is reported in [16], implements the single-bit quantizer. The autozero technique is applied to the first amplifier.…”

“…The changes required to the TMOS sensor are minimal and do not impact significantly its sensitivity. The proposed bias and readout circuit for the reference pixels employs a twophase time-domain architecture [16], which provides biasing to the sensing element by alternatively switching between two different bias current values in subsequent phases. The subtraction operation between the voltage signal found at two subsequent phases, resulting in a proportional-to-absolutetemperature (PTAT) dependency, and the temperature-todigital conversion are performed by means of switchedcapacitor 1-bit second-order Σ∆ ADC.…”