A Multi-Context Neural Core Design for Reconfigurable Neuromorphic Arrays

Foshie, Adam Z.; Chakraborty, Nishith N.; Murray, J.; Fowler, Tanner J.; Shawkat, Mst Shamim Ara; Rose, Garrett S.

doi:10.1109/isvlsi51109.2021.00023

Cited by 6 publications

(1 citation statement)

References 22 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…STDP has been integrated into hardware through various means, including digital circuits [9,10], analog circuits [11], and memristor circuits [12]. Among these, memristors stand out as promising choices for implementing STDP due to their adaptable weight storage capabilities [13].…”

Section: Introductionmentioning

confidence: 99%

Hardware software co-design for leveraging STDP in a memristive neuroprocessor

Chakraborty,

Ameli,

Das

et al. 2024

Neuromorph. Comput. Eng.

View full text Add to dashboard Cite

In neuromorphic computing, different learning mechanisms are being widely adopted to improve the performance of a specific application. Among these techniques, Spike-Timing-Dependent Plasticity (STDP) stands out as one of the most favored. STDP is simply managed by the temporal information of an event, which is biologically inspired. However, most of the prior works on STDP are focused on circuit implementation or software simulation for performance evaluation. Previous works also lack a comparative analysis of the performances of different STDP implementations. This study aims to provide a comprehensive assessment of STDP, centering on the performance across various applications such as classification (static and temporal datasets), control, and reservoir computing. Different applications necessitate distinct STDP configurations to achieve optimal performance with the neuroprocessor. Additionally, this work introduces an Application-Specific Integrated Circuit (ASIC) design of STDP circuitry. The design is based on current-controlled memristive synapse principles and utilizes 65nm CMOS technology from IBM. The detailed presentation includes circuitry specifics, layout, and performance parameters such as energy consumption and design area.

show abstract

Section: Introductionmentioning

confidence: 99%

Hardware software co-design for leveraging STDP in a memristive neuroprocessor

Chakraborty,

Ameli,

Das

et al. 2024

Neuromorph. Comput. Eng.

View full text Add to dashboard Cite

show abstract

Enhanced read resolution in reconfigurable memristive synapses for Spiking Neural Networks

Das,

Schuman,

Chakraborty

et al. 2024

Sci Rep

Self Cite

View full text Add to dashboard Cite

The synapse is a key element circuit in any memristor-based neuromorphic computing system. A memristor is a two-terminal analog memory device. Memristive synapses suffer from various challenges including high voltage, SET or RESET failure, and READ margin issues that can degrade the distinguishability of stored weights. Enhancing READ resolution is very important to improving the reliability of memristive synapses. Usually, the READ resolution is very small for a memristive synapse with a 4-bit data precision. This work considers a step-by-step analysis to enhance the READ current resolution or the read current difference between two resistance levels for a current-controlled memristor-based synapse. An empirical model is used to characterize the $${\hbox {HfO}}_{2}$$ HfO 2 based memristive device. $$1\textrm{st}$$ 1 st and $$2\textrm{nd}$$ 2 nd stage device of our proposed synapse design can be scaled to enhance the READ current margin up to $$\sim$$ ∼ 4.3$$\times$$ × and $$\sim$$ ∼ 21%, respectively. Moreover, READ current resolution can be enhanced with run-time adaptation techniques such as READ voltage scaling and body biasing. The READ voltage scaling and body biasing can improve the READ current resolution by about 46% and 15%, respectively. TENNLab’s neuromorphic computing framework is leveraged to evaluate the effect of READ current resolution on classification, control, and reservoir computing applications. Higher READ current resolution shows better accuracy than lower resolution even when facing different levels of read noise.

show abstract

A system design perspective on neuromorphic computer processors

Rose¹,

Shawkat²,

Foshie³

et al. 2021

Neuromorph. Comput. Eng.

View full text Add to dashboard Cite

Neuromorphic computing has become an attractive candidate for emerging computing platforms. It requires an architectural perspective, meaning the topology or hyperparameters of a neural network is key to realizing sound accuracy and performance in neural networks. However, these network architectures must be executed on some form of computer processor. For machine learning, this is often done with conventional computer processing units, graphics processor units, or some combination thereof. A neuromorphic computer processor or neuroprocessor, in the context of this paper, is a hardware system that has been designed and optimized for executing neural networks of one flavor or another. Here, we review the history of neuromorphic computing and consider various spiking neuroprocessor designs that have emerged over the years. The aim of this paper is to identify emerging trends and techniques in the design of such brain-inspired neuroprocessor computer systems.

show abstract

A Multi-Context Neural Core Design for Reconfigurable Neuromorphic Arrays

Cited by 6 publications

References 22 publications

Hardware software co-design for leveraging STDP in a memristive neuroprocessor

Hardware software co-design for leveraging STDP in a memristive neuroprocessor

Enhanced read resolution in reconfigurable memristive synapses for Spiking Neural Networks

A system design perspective on neuromorphic computer processors

Contact Info

Product

Resources

About