A Multi-Context Pipelined Array for Embedded Systems

Abstract

The integration of a reconfigurable device into complex SoCs is a common request aimed at adding software programmable efficient computational blocks to a system. In such environment a traditional approach in FPGA design could not meet the need for an easy-to-use and easy-to-integrate device. This paper presents the PiCoGA-II reconfigurable datapath which has been designed as a multi-context array to provide fast dynamic reconfiguration. Architectural choices to reduce the area overhead of this approach are described. A reconfigurable dedicated control unit provides a clear interface for an easy integration of the device together with a hardware support for a programming flow starting from a sequential high-level language. The logic cells have been redesigned with respect to the previous version, to improve their computational efficiency and flexibility. The PiCoGA-II has been fabricated in 0.13µm CMOS technology. The implementation of several MPEG-2 kernels shows that the multi-context array has a computational density which is 2x higher than an equivalent single-context one and is 2x higher than a Virtex-II FPGA when all the 4 contexts are utilized.

An integrated tool flow to realize runtime-reconfigurable applications on a new class of partial multi-context FPGAs

“…in [7,8,9]. Typically, context switching is assumed for all configuration bits of an architecture, e.g.…”

Row-based configuration mechanism for a 2-D processing element array in coarse-grained reconfigurable architecture

“…In the hybrid one, while a part of the contexts are statically reconfigurable, the others are dynamically reconfigurable, like RaPiD. From a context size perspective, evolution of the configuration has taken place over three periods along with the increasing complexity of applications: singlecontext [18,19], multi-context [20][21][22], and configuration cache [12,23]. The number of operations in computational kernels is smaller, several times larger and many times larger than the dimension of the array in the three periods respectively.…”

Hierarchical representation of on-chip context to reduce reconfiguration time and implementation area for coarse-grained reconfigurable architecture

“…Applications that were smaller than the dimension of the RPU could be loaded into a single context plane and accelerated effectively. In the second period, a multi-context structure was proposed [3][4][5]. To some extent, this resolved the problem of executing large applications on the RPU by involving more configuration planes.…”