A multi-dimensional packet classifier for NP-based firewalls

Rashti, Mohammad Javad; Rabiee, Hamid R.; Foroutan, A.; Lavasani, Maysam

doi:10.1109/saint.2004.1266123

Cited by 4 publications

(3 citation statements)

References 4 publications

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“…The classifier processes the five main header fields, as typically adopted in the literature and in real classifiers [21] for identifying a microflow: the IP destination and source addresses, and layer 4 destination and source ports and protocol type. Moreover, we have modified the original version of the algorithm [22] to address the hardware platform constraints, especially in terms of memory consumption. In detail, to decrease the memory requirements when there is a rule with non-specified parts, the asterisk-state has been created: it includes all the states hidden by the wild-card in a field specification, without the need for nodes explosion.…”

Section: -Es Application Schemementioning

confidence: 99%

A network processor‐based architecture for multi‐gigabit traffic analysis

Pietro

Ficara

Giordano

et al. 2009

Int J Communication

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SUMMARYThe wide availability of cheap and effective commodity PC hardware has driven the development of versatile traffic monitoring software such as protocol analyzers, traffic characterizers and intrusion detection systems. Most of them are designed to run on general purpose architectures and are based on the well-known libpcap API, which has rapidly become a de facto standard. Although many improvements have been applied to packet capturing software, it still suffers from several performance flaws, mainly due to the underlying hardware bottlenecks. To overcome these issues, this paper proposes a system architecture, which combines the high performance of a Network Processor card with the flexibility of software-based solutions. It allows for removing most part of the hardware limitations exhibited by a purely PC-based architecture, while preserving the full compliance to any software applications based on libpcap. In addition, the proposed system enables the use of monitoring applications at the wire speed, with the possibility of on-the-fly data processing. The system performance has been thoroughly assessed: the results show that it clearly outperforms the previous PC-based solutions in terms of packet capturing power, while the timestamping accuracy is as good as that achieved by DAG cards.

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Section: -Es Application Schemementioning

confidence: 99%

A network processor‐based architecture for multi‐gigabit traffic analysis

Pietro

Ficara

Giordano

et al. 2009

Int J Communication

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“…Rashti et al [8] present a multidimensional packet classifier engine for NP-based firewalls, established on a hierarchical trie algorithm and on a technique of memory usage optimization. Srinivasan and Feng [9] study the performance of two different design mappings of the bit vector algorithm on the Intel IXP1200 NP.…”

Section: Related Workmentioning

confidence: 99%

“…Concerning the fulfillment of a classification engine on top of NPs, Kounavis et al [7] analyze several databases of classification rules and derive their statistical properties, in order to suggest a classification architecture to be implemented efficiently on NPs. Rashti et al [8] present a multidimensional packet classifier engine for NP-based firewalls, established on a hierarchical trie algorithm and on a technique of memory usage optimization. Srinivasan and Feng [9] study the performance of two different design mappings of the bit vector algorithm on the Intel IXP1200 NP.…”

Section: Related Workmentioning

confidence: 99%

REFINE: The reconfigurable packet filtering on network processor

Ficara

Giordano

Rossi³

et al. 2008

Int J Communication

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SUMMARYNetwork processors (NPs) are emerging as very promising platforms for developing reconfigurable and high-performance network devices, due to their capability to combine the flexibility of general-purpose processors with the high-performance features of hardware-based systems. They represent the most suitable solutions for implementing complex and dynamic tasks, such as packet classification and scheduling, which are key operations, for example, in DS networks. Programmability and reconfigurability allow NP-based devices to be continuously adapted to the new network requirements, obtaining a high time in market.This paper illustrates the compound process that leads to the implementation of a reconfigurable multidimensional packet filtering on the Intel R IXP2400 NP. The multidimensional multibit trie is chosen as the best algorithm to be implemented and it is modified to exploit the specific features of NP. The different tasks are mapped on the NP computational resources and an optimized implementation is performed, with subsequent experimental validation.

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Chen

Hwang

et al. 2008

Int J Communication

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A multi-dimensional packet classifier for NP-based firewalls

Cited by 4 publications

References 4 publications

A network processor‐based architecture for multi‐gigabit traffic analysis

A network processor‐based architecture for multi‐gigabit traffic analysis

REFINE: The reconfigurable packet filtering on network processor

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