A multi-level architecture for hardware Trojan and vulnerability runtime detection and response towards cryptographic IP

Abstract

Existing functional validation approaches and postmanufacturing tests are inadequate to detect all hardware bugs and hardware Trojans in third-party intellectual property blocks (3PIPs). Especially for cryptographic IPs, a well-designed framework is needed for detecting and mitigating hardware security risks even after chip deployment. In this paper, we present an innovative multi-level architecture providing runtime hardware security detection and response. The proposed architecture consists of a controller and a security wrapper, enabling the collaborative operation of three different types of detection and three levels of response according to the potential malicious impact. We show that a field programmable gate array prototype of the proposed architecture can pursue 4 hardware bug and 6 hardware Trojan detection towards an AES IP, and make appropriate protective responses.

DHRCA: A Design of Security Architecture Based on Dynamic Heterogeneous Redundant for System on Wafer

“…Runtime protection techniques are the last line of defense against HT attacks, which can be categorized into runtime monitoring and runtime tolerance techniques. Dong et al [15] designed a multilevel architecture to protect third-party encrypted IP by secure wrapper and controller. The wrapper checks the input and output signals of the IP, and the controller configures different levels of response measures based on the results of the wrapper to mitigate the security issues of the encrypted IP.…”