A multi-measurements RO-TDC implemented in a Xilinx field programmable gate array

Fine resolution delay tuning method to improve the linearity of an unbalanced time‐to‐digital converter on a Xilinx FPGA

“…The architecture of the MMRO‐TDC proposed in [16] measures relative time intervals between multiple signals under test. In the simplified version shown in Fig.…”

“…Apart from saving logic resources, the RO‐TDC architecture helps to improve the linearity of the TDC. Recently, we proposed a multi‐measurement RO‐TDC (MMRO‐TDC) implemented in a Xilinx FPGA [16]. This architecture was supported by a compact implementation suitable for multiple simultaneous measurements.…”

Digital instrument with configurable hardware and firmware for multi-channel time measures

“…Programmable logic devices, especially FPGA and SoC, allow us to implement TDCs with different kinds of structures. Looking into the literature, we can roughly divide these architectures between TDCs based on feedback (FB) circuits, 34,35 e.g., ring-oscillators, and feedforward (FF) ones based on delay-lines. [34][35][36] The high difference of propagation delay values among combinatorial logic elements, mainly due to the scaling down of technology, favors the implementation of feedforward solutions with respect to the feedback ones.…”

“…Looking into the literature, we can roughly divide these architectures between TDCs based on feedback (FB) circuits, 34,35 e.g., ring-oscillators, and feedforward (FF) ones based on delay-lines. [34][35][36] The high difference of propagation delay values among combinatorial logic elements, mainly due to the scaling down of technology, favors the implementation of feedforward solutions with respect to the feedback ones. To confirm this, we can consider the worsening in resolution from 5 ps to 63.3 ps shown by two TDCs based on a ring-oscillator implemented in 28-nm 34 and 90-nm 35 technology, respectively.…”

“…[34][35][36] The high difference of propagation delay values among combinatorial logic elements, mainly due to the scaling down of technology, favors the implementation of feedforward solutions with respect to the feedback ones. To confirm this, we can consider the worsening in resolution from 5 ps to 63.3 ps shown by two TDCs based on a ring-oscillator implemented in 28-nm 34 and 90-nm 35 technology, respectively. Differently, a TDC based on delay-line offers a resolution of 75 ps in 130-nm, 36 50 ps in 90-nm, 37 and 39 The different propagation times of signals through the cascaded bins constituting a delay-line implemented in a FPGA device causes not uniform quantization.…”