A Multi-Thread Processor Architecture Based on the Continuation Model

Matsuzaki, Takanori; Amamiya, Satoshi; Izumi, Masaaki; Amamiya, Makoto

doi:10.1109/iwia.2005.22

Cited by 2 publications

(2 citation statements)

References 5 publications

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“…Fuce processor executes fine-grain non-preemptive threads and most features necessary to implement our operating system with zero-wait threads are provided at its hardware level. Since typical technical issues which are common in user applications are already discussed in another work [15], we discuss implementation issues of operating systems on Fuce focusing on handling I/O requests in this paper.…”

Section: Operating System On Fucementioning

confidence: 99%

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OS Mechanism for Continuation-based Fine-grained Threads on Dedicated and Commodity Processors

Kusakabe

Yamada

Aono

et al. 2007

2007 IEEE International Parallel and Distributed Processing Symposium

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Section: Operating System On Fucementioning

confidence: 99%

“…(See Figure 1) One is Fuce (FUsion Communication and Execution) processor architecture, which is dedicated to fine-grained multithreading [15], and the other is commodity processors such as Intel x86.…”

Section: Introductionmentioning

confidence: 99%

OS Mechanism for Continuation-based Fine-grained Threads on Dedicated and Commodity Processors

Kusakabe

Yamada

Aono

et al. 2007

2007 IEEE International Parallel and Distributed Processing Symposium

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Simulation and Verification of Self Test 16Bit Processor

Pradhan¹

2011

IJCA

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This paper presents the design and verification of 16 bit processor. The Booth multiplier and restoring division are integrated in to the ALU of the proposed processor. The processor is described in structural level to verify the general understanding of the system. The processor has 16-bit instruction based on three different format R-format, I-format and J-format. The control unit generates all the control signals needed to control the coordination among the entire component of the processor. All the modules in the design are coded in VHDL (very high speed integrated circuit hardware description language) to ease the description, verification, simulation and hardware implementation. The design entry, synthesis, and simulation of processor are done by using Xilinx ISE 10.1 software and implemented on XC2S200-6pq208 Spartan-II FPGA device. General TermsBooth Algorithms, Restoring division Algorithm. KeywordsRegister transfer level, Reduced instruction set computer, Very high speed integrated circuit hardware description language , Arithmetic logic unit, Field programmable gate array.

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A Multi-Thread Processor Architecture Based on the Continuation Model

Cited by 2 publications

References 5 publications

OS Mechanism for Continuation-based Fine-grained Threads on Dedicated and Commodity Processors

OS Mechanism for Continuation-based Fine-grained Threads on Dedicated and Commodity Processors

Simulation and Verification of Self Test 16Bit Processor

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