A multipath network-on-chip topology

Ray, Kaushik; Kalita, Alakesh; Biswas, Abhijit; Hussain, Md. Anwar

doi:10.1109/icices.2016.7518839

Cited by 3 publications

(1 citation statement)

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“…This architectural strategy employs a growing number of functional modules, thereby enhancing overall system functionality and performance. These modules collaborate seamlessly, efficiently executing tasks, and communicating via a shared bus to distribute workloads and meet performance benchmarks [4,5].…”

Section: Introductionmentioning

confidence: 99%

An Energy-Efficient Routing Protocol for a Modified Fat-Tree Topology in System-on-Chip Design

Yadav,

Ahmed,

Ambudkar

et al. 2023

MMEP

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The rapid evolution of integration technology has significantly influenced System-on-Chip (SoC) design, characterized by the unprecedented integration of numerous functional modules onto ever-shrinking chips. Consequently, facilitating robust communication between these burgeoning modules has become critical to optimizing system functionality and performance. Traditional Bus architecture, however, proves inadequate in realizing this goal. To circumvent these communication impediments, mesh and torus interconnected architectures have been proposed, with cores interconnected within a single chip using diverse routing strategies for seamless operation. This study investigates a deterministic, deadlock-free routing protocol for a modified Fat-Tree topology that incorporates a core module at the intermediate level.Utilizing the Sniper simulator environment for evaluation, it is demonstrated that the proposed protocol surpasses the X-Y routing method used in both mesh and torus topologies in terms of power efficiency and throughput. The results show a 4%-8% reduction in power consumption compared to other approaches, indicating the superior efficacy of the proposed method.

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Section: Introductionmentioning

confidence: 99%