A Multiplierless 2-D Convolver Chip for Real-Time Image Processing

Sunwoo, Myung Hoon; Oh, Sangchul

doi:10.1023/b:vlsi.0000028534.35761.a8

Cited by 16 publications

(10 citation statements)

References 18 publications

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“…The resulting architecture based on equation 4 contains same M number of shiftadd-accumulate blocks as multipliers in conventional FIR (Fig.1). This can be simplified further [11] to equation 5 for area critical implementation resulting in the following:…”

Section: Proposed Fir Architecturementioning

confidence: 99%

Subthreshold FIR Filter Architecture for Ultra Low Power Applications

Mishra

Al-Hashimi

2009

Lecture Notes in Computer Science

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Abstract. Subthreshold design has been proposed as an effective technique for designing signal processing circuits needed in wireless sensor nodes powered by sources with limited energy. In this paper we propose a subthreshold FIR architecture which brings the benefits of reduced leakage energy, reduced minimum energy point, reduced operating voltage and increased operating frequency when compared with recently reported subthreshold designs. We shall demonstrate this through the design of a 9-tap FIR filter operating at 220mV with operational frequency of 126kHz/sample consuming 168.3nW or 1.33pJoules/sample. Furthermore, the area overhead of the proposed method is less than that of the transverse structure often employed in subthreshold filter designs. For example, a 9-tap filter based on transverse structure has 5× higher area than the filter designed using our proposed method.

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Section: Proposed Fir Architecturementioning

confidence: 99%

Subthreshold FIR Filter Architecture for Ultra Low Power Applications

Mishra

Al-Hashimi

2009

Lecture Notes in Computer Science

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“…Second method is using multiplierless 2-D convolver, Myung H. Sunwoo [7] proposed using shifter and accumulator to replace the multiplier, although their convolver can outperform HSP48901 and HSP48908, however, Samsung's chip has limitation on kernel size.…”

Section: Advantages and Disadvantages Of Using Electronic Correlatormentioning

confidence: 99%

System Comparison of Electronic and Optical Correlator

Lee¹

2010

J Sign Process Syst

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During the past three decades, optical information processing has received a lot of attention from large number of engineers and physicists. Although both optical coherent and incoherent processing can be employed for optical correlation and convolution, and wide variety of information processing functions can be performed, however, several new faster approaches to VLSI implementation of electronic cross correlation or convolution have been demonstrated recently. Due to increasingly importance of correlator in apply to digital image processing, stereo matching, and pattern recognition. In this paper, we perform a comparison between the electronic and optical correlator in terms of several system parameters, such as timing, area and power consumption. Such comparison may assist the system planner in actual implementation

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“…For substitute algorithms that improve the efficiency of convolution kernel modules [4][5][6][7], the computational complexity and hardware consumption will shrink in proportion with the number of MSAs by applying a recurrent decomposition. Thus, these schemes can benefit from RD architectures.…”

Section: Discussionmentioning

confidence: 99%

“…Note that the benefits apply to all MSAs types (e.g. SA [4], LUT [5], and log 2 and inverse-log 2 approximations [6]), as their computational complexities all reduce proportionally with the number of MSAs.…”

Section: A Fpga Implementationmentioning

confidence: 99%

“…These schemes sacrifices processing speed in order to reduce hardware consumption. A second category of methods replaces the multipliers with alternatives, such as shift-and-accumulation (SA) operations [4], look up table (LUT) [5], and log 2 and inverse-log 2 approximations [6]. However, the total number of multiplications or substitute algorithms (MSAs) remains untouched in these multiplier-less implementations.…”

Section: Introductionmentioning

confidence: 99%

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Recurrently Decomposable 2-D Convolvers for FPGA-Based Digital Image Processing

Yang

Bharath

2016

IEEE Trans. Circuits Syst. II

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Abstract-Two-dimensional (2-D) convolution is a widely used operation in image processing and computer vision, characterized by intensive computation and frequent memory accesses. Previous efforts to improve the performance of field-programmable gate array (FPGA) convolvers focused on the design of buffering schemes and on minimizing the use of multipliers. A recently proposed recurrently decomposable (RD) filter design method can reduce the computational complexity of 2-D convolutions by splitting the convolution between an image and a large mask into a sequence of convolutions using several smaller masks. This brief explores how to efficiently implement RD based 2-D convolvers using FPGA. Three FPGA architectures are proposed based on RD filters, each with a different buffering scheme. The conclusion is that RD based architectures achieve higher area efficiency than other previously reported state-of-the-art methods, especially for larger convolution masks. An area efficiency metric is also suggested, which allows the most appropriate architecture to be selected.Index Terms-Field-programmable gate arrays (FPGAs), large convolution mask, recurrently decomposable, two-dimensional (2-D) convolution.

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A Multiplierless 2-D Convolver Chip for Real-Time Image Processing

Cited by 16 publications

References 18 publications

Subthreshold FIR Filter Architecture for Ultra Low Power Applications

Subthreshold FIR Filter Architecture for Ultra Low Power Applications

System Comparison of Electronic and Optical Correlator

Recurrently Decomposable 2-D Convolvers for FPGA-Based Digital Image Processing

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