A Multiscale Simulation Framework for Steep-Slope Si Nanowire Cold Source FET

Gan, Weizhuo; Luo, Kun; Qi, Guodong; Prentki, Raphaël; Liu, Fei; Huo, Jiali; Huang, Weixing; Bu, Jianhui; Zhang, Qingzhu; Guo, Hong; Lü, Ye; Wu, Zhenhua

doi:10.1109/ted.2021.3083602

Cited by 6 publications

(1 citation statement)

References 39 publications

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“…[138] Weizhuo Gan and coworkers realized a Si cold source FET (CSFET) by a broken-gap-like p-Si/metal/n-Si cold source (CS), which cut off thermal tail of carriers by bandgap and suppressed the hot carriers injection, leading to a steeper SS, [139] correspondingly, a reverse typed Si CSFET could be realized by n-Si/metal/p-Si broken band structures, which was also sufficiently studied to obtain a sub-thermionic SS. [140] 3D Dirac source materials mainly aim at achieving steep switching behavior in Si based FET by engineering source DOS to cut off thermal tail of high energy carriers to suppress hot carriers injection, which is relatively compatible with modern Si fabrication process in compared with DSFETs based on 2D materials. Albeit promising as 3D DSFETs are to be applied in modern Si industry, it is hard to fabricate 3D DSFET being free of interface states that may smear out the steep switching introduced by cold injection by Dirac source, thus, there are scarce experimental reports of 3D DSFETs based on superlattices or Si broken band alignment Dirac structures.…”

Section: Current Status Of 2d Dsfetmentioning

confidence: 99%

Steep Slope Field Effect Transistors Based on 2D Materials

Qin,

Tian,

et al. 2024

Adv Elect Materials

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With field effect transistor (FET) sustained to downscale to sub‐10 nm nodes, performance degradation originates from short channel effects (SCEs) degradation and power consumption increment attributed to inhibition of supply voltage (VDD) scaling down proportionally caused by thermionic limit subthreshold swing (SS) (60 mV dec−1) pose substantial challenges for today's semiconductor industry. To further sustain the Moore's law life, incorporation of new device concepts or new materials are imperative. 2D materials are predicted to be able to combat SCEs by virtue of high carrier mobility maintainability regardless of thickness thinning down, dangling bonds free surface and atomic thickness, which contributes to super gate electrostatic controllability. To overcome increasing power dissipation problem, new device structures including negative capacitance FET (NCFET), tunnel FET (TFET), dirac source FET (DSFET) and the like, which show superiority in decreasing VDD by lowering SS below thermionic limit of 60 mV dec−1 have been brought out. The combination of 2D materials and ultralow steep slope device structures holds great promise for low power‐dissipation electronics, which encompass both suppressed SCEs and reduced VDD simultaneously, leading to improved device performance and lowered power dissipation.

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Section: Current Status Of 2d Dsfetmentioning

confidence: 99%

Steep Slope Field Effect Transistors Based on 2D Materials

Qin,

Tian,

et al. 2024

Adv Elect Materials

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Cold source field-effect transistors: Breaking the 60-mV/decade switching limit at room temperature

Wang

Zhi

et al. 2023

Physics Reports

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Phonon-assisted charge carriers thermalization in semiconductor Si and metallic silicide NiSi2, CoSi2: A non-adiabatic molecular dynamics study

Luo,

Gan,

Hou

et al. 2024

Journal of Applied Physics

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Recently, the cold source field-effect transistor (CSFET) has emerged as a promising solution to overcome Boltzmann tyranny in its ballistic regime, offering a steep-slope subthreshold swing (SS) of less than 60 mV/decade. However, challenges arise due to scattering, particularly from inelastic scattering, which can lead to significant degradation in SS through cold carrier thermalization. In this study, we delve into the theoretical investigation of the electronic excitation/relaxation dynamic process using the state-of-the-art nonadiabatic molecular dynamics (NAMD) method. The mixed quantum-classical NAMD proves to be a powerful tool for comprehensively analyzing cold carrier thermalization and transfer processes in semiconductor Si, as well as metallic silicides (NiSi2 and CoSi2). The approach of mixed quantum-classical NAMD takes into account both carrier decoherence and detailed balance, enabling the calculation of thermalization factors, relaxation times, scattering times, and scattering rates at various energy levels. The thermalization of carriers exhibits a gradual increase from low to high energy levels. Achieving partial thermalization from the ground state to reach the thermionic current window occurs within a sub-100 fs time scale. Full thermalization across the entire energy spectrum depends sensitively on the barrier height, with the scattering rate exponentially decreasing as the energy of the out-scattering state increases. Notably, the scattering rate of NiSi2 and CoSi2 is two orders of magnitude higher than that of Si, attributed to their higher density of states compared to Si. This study not only provides insights into material design for low-power tunnel field-effect transistors but also contributes valuable information for advancing CSFET in emerging technologies.

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A Multiscale Simulation Framework for Steep-Slope Si Nanowire Cold Source FET

Cited by 6 publications

References 39 publications

Steep Slope Field Effect Transistors Based on 2D Materials

Steep Slope Field Effect Transistors Based on 2D Materials

Cold source field-effect transistors: Breaking the 60-mV/decade switching limit at room temperature

Phonon-assisted charge carriers thermalization in semiconductor Si and metallic silicide NiSi2, CoSi2: A non-adiabatic molecular dynamics study

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