With the development of machine learning technology, the exploration of energy-efficient and flexible architectures for object inference algorithms is of growing interest in recent years. However, not many publications concentrate on coarsegrained reconfigurable architecture (CGRA) for object inference algorithms. This paper provides a stream processing, dual-track programming CGRA-based approach to address the inherent computing characteristics of algorithms in object inference. Based on the proposed approach, an architecture called SDT-CGRA is presented as an implementation prototype. To evaluate the performance, the SDT-CGRA is realized in Verilog HDL and implemented in SMIC 55nm process, with the footprint of 5.19 mm 2 at 450 MHz. Seven object inference algorithms including CNN, k-means, PCA, SPM, linear-SVM, Softmax and Joint-Bayesian are selected as benchmarks. The experimental results show that the SDT-CGRA can gain on average 343.8 times and 17.7 times higher energy efficiency for Softmax, PCA and CNN, 621.0 times and 1261.8 times higher energy efficiency for k-means, SPM, linear-SVM and Joint-Bayesian algorithms when compared to the Intel Xeon E5-2637 CPU and the Nvidia TitanX GPU. When compared to the state-of-ther-art solutions of AlexNet on FPGA and CGRA, the proposed SDT-CGRA can achieve a 1.78 times increase in energy efficiency and a 13 times speedup respectively.