A Multithreaded Multicore System for Embedded Media Processing

Hoogerbrugge, Jan; Terechko, Andrei

doi:10.1007/978-3-642-19448-1_9

Cited by 24 publications

(24 citation statements)

References 13 publications

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“…The 2D-Wave parallelization strategy has already been implemented in this decoder [15], making it a perfect starting point for the implementation of the 3D-Wave. The NXP H.264 decoder is highly optimized, including both machinedependent optimizations (e.g.…”

Section: Methodsmentioning

confidence: 99%

A Highly Scalable Parallel Implementation of H.264

Azevedo

Juurlink

Meenderinck

et al. 2011

Lecture Notes in Computer Science

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Abstract. Developing parallel applications that can harness and efficiently use future many-core architectures is the key challenge for scalable computing systems. We contribute to this challenge by presenting a parallel implementation of H.264 that scales to a large number of cores. The algorithm exploits the fact that independent macroblocks (MBs) can be processed in parallel, but whereas a previous approach exploits only intra-frame MB-level parallelism, our algorithm exploits intra-frame as well as inter-frame MB-level parallelism. It is based on the observation that inter-frame dependencies have a limited spatial range. The algorithm has been implemented on a many-core architecture consisting of NXP TriMedia TM3270 embedded processors. This required to develop a subscription mechanism, where MBs are subscribed to the kick-off lists associated with the reference MBs. Extensive simulation results show that the implementation scales very well, achieving a speedup of more than 54 on a 64-core processor, in which case the previous approach achieves a speedup of only 23. Potential drawbacks of the 3D-Wave strategy are that the memory requirements increase since there can be many frames in flight, and that the frame latency might increase. Scheduling policies to address these drawbacks are also presented. The results show that these policies combat memory and latency issues with a negligible effect on the performance scalability. Results analyzing the impact of the memory latency, L1 cache size, and the synchronization and thread management overhead are also presented. Finally, we present performance requirements for entropy (CABAC) decoding.

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Section: Methodsmentioning

confidence: 99%

A Highly Scalable Parallel Implementation of H.264

Azevedo

Juurlink

Meenderinck

et al. 2011

Lecture Notes in Computer Science

Self Cite

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“…Some hardware support solutions have been proposed to speed-up task management, such as Carbon [6], TriMediabased multi-core system [7] and TMU [8], but most of them only schedule independent tasks. In these systems, the programmer is responsible for delivering tasks at the appropriate time.…”

Section: Related Workmentioning

confidence: 99%

Picos: A hardware runtime architecture support for OmpSs

Yazdanpanah

Álvarez

Jiménez-González

et al. 2015

Future Generation Computer Systems

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OmpSs is a programming model that provides a simple and powerful way of annotating sequential programs to exploit heterogeneity and task parallelism based on runtime data dependency analysis, dataflow scheduling and out-of-order task execution; it has greatly influenced Version 4.0 of the OpenMP standard. The current implementation of OmpSs achieves those capabilities with a puresoftware runtime library: Nanos++. Therefore, although powerful and easy to use, the performance benefits of exploiting finegrained (pico) task parallelism are limited by the software runtime overheads. To overcome this handicap we propose Picos, an implementation of the Task Superscalar (TSS) architecture that provides hardware support to the OmpSs programming model. Picos is a novel hardware dataflow-based task scheduler that dynamically analyses inter-task dependencies and identifies task-level parallelism at run-time. In this paper, we describe the Picos Hardware Design and the latencies of the main functionality of its components, based on the synthesis of their VHDL design. We have implemented a full cycle-accurate simulator based on those latencies to perform a design exploration of the characteristics and number of its components in a reasonable amount of time.Finally, we present a comparison of the Picos and Nanos++ runtime performance scalability with a set of real benchmarks. With Picos, a programmer can achieve ideal scalability using aggressive parallel strategies with a large number of fine granularity tasks.

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“…In this work, as in [10,12,17], only the MB processing is parallelized. We assume that either an entropy decoding accelerator exists or that the entropy decoding has been parallelized at the slice level.…”

Section: Decouple Entropy Decodingmentioning

confidence: 99%

“…The first two of the three are variants of the TP implementation, Tail Submit (TS) [10] and a strategy referred to as Multiple Task (MT), which add opportunities for prefetching. In TS it is assumed that the next MB to process is the MB to the right of the current.…”

Section: Qualitative Evaluationmentioning

confidence: 99%

Evaluation of parallel H.264 decoding strategies for the Cell Broadband Engine

Ching

Juurlink

Meenderinck

2010

Proceedings of the 24th ACM International Conference on Supercomputing

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How to develop efficient and scalable parallel applications is the key challenge for emerging many-core architectures. We investigate this question by implementing and comparing two parallel H.264 decoders on the Cell architecture. It is expected that future many-cores will use a Cell-like local store memory hierarchy, rather than a non-scalable shared memory. The two implemented parallel algorithms, the Task Pool (TP) and the novel Ring-Line (RL) approach, both exploit macroblock-level parallelism. The TP implementation follows the master-slave paradigm and is very dynamic so that in theory perfect load balancing can be achieved. The RL approach is distributed and more predictable in the sense that the mapping of macroblocks to processing elements is fixed. This allows to better exploit data locality, to overlap communication with computation, and to reduce communication and synchronization overhead. While TP is more scalable in theory, the actual scalability favors RL. Using 16 SPEs, RL obtains a scalability of 12x, while TP achieves only 10.3x. More importantly, the absolute performance of RL is much higher. Using 16 SPEs, RL achieves a throughput of 139.6 frames per second (fps) while TP achieves only 76.6 fps. A large part of the additional performance advantage is due to hiding the memory latency. From the results we conclude that in order to fully leverage the performance of future many-cores, a centralized master should be avoided and the mapping of tasks to cores should be predictable in order to be able to hide the memory latency.

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A Multithreaded Multicore System for Embedded Media Processing

Cited by 24 publications

References 13 publications

A Highly Scalable Parallel Implementation of H.264

A Highly Scalable Parallel Implementation of H.264

Picos: A hardware runtime architecture support for OmpSs

Evaluation of parallel H.264 decoding strategies for the Cell Broadband Engine

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