A NAND Flash Memory Controller for SD/MMC Flash Memory Card

Lin, Chuan-Sheng; Chen, Kuang-Yuan; Wang, Yu-Hsian; Dung, Lan‐Rong

doi:10.1109/icecs.2006.379716

Cited by 7 publications

(3 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Lin and Dung [5] proposed A NAND flash memory controller for SD/MMC flash memory card. They designed a t-EC w-bit parallel BCH ECC to correct the bit-flipping errors.…”

Section: B Related Workmentioning

confidence: 99%

A Scalable Multi-channel Parallel NAND Flash Memory Controller Architecture

Xiao

Lai

2011

2011 Sixth Annual Chinagrid Conference

View full text Add to dashboard Cite

With more data-intensive applications appearing in the present social life, the NAND flash memory acting as a replacement candidate of hard disk drives is popularly used in some data centers due to its lower power consumption, faster random access, and higher shock resistance. But the traditional solid state disk exposes the limitation of bandwidth. To this end, we deliver the scalable multichannel flash memory controller architecture in this paper to exploit the parallelism of multiple chips. It supports all the flash operations, and boosts the performance by evenly distributing multiple accesses among different chips when using the error correction code to improve its reliability. The functions of the multi-channel parallel controller are validated according to a wide spread of workloads. And the evaluation results show that our proposed eight-channel controller outperforms the traditional controller by more than three times and can be well scaled to be 128 channels without extra critical timing path.

show abstract

“…Lin and Dung [5] proposed A NAND flash memory controller for SD/MMC flash memory card. They designed a t-EC w-bit parallel BCH ECC to correct the bit-flipping errors.…”

Section: B Related Workmentioning

confidence: 99%

A Scalable Multi-channel Parallel NAND Flash Memory Controller Architecture

Xiao

Lai

2011

2011 Sixth Annual Chinagrid Conference

View full text Add to dashboard Cite

show abstract

“…Latest overall structure of NAND flash device is looks very similar to its conventional structure. A NAND flash controller implements memory mapped interface [10]. A multiplane array packs contains its own set of Cache/Data registers, more memory cells on a die and partitioned it into several plans.…”

Section: Nand Flash Memroy Controller Architechturementioning

confidence: 99%

Verification and Simulation of New Designed NAND Flash Memory Controller

Agarwal

Magraiya

Saxena³

2013

2013 International Conference on Communication Systems and Network Technologies

View full text Add to dashboard Cite

“…The flash memory access controller is one which communicates with flash memory controller. An improvement on the flash memory controller designed in [4] gives a higher rate of data access. Such designs definitely improve the performance of a flash memory access controller.…”

Section: Introductionmentioning

confidence: 99%

Data concentration and archival to SD card via hardware description language

Elkeelany

Todakar

2011

2011 IEEE GLOBECOM Workshops (GC Wkshps)

View full text Add to dashboard Cite

Smart Grid (SG) is the next generation's power grid system. Delivering control, monitoring and management data to grid elements often requires the efficient archival of acquired information. The main objective of this research is to design an experimental platform for efficient, on-chip, real-time data concentrator for accessing data from a Secure Digital flash memory card using the SD bus protocol. All the hardware design is done using Verilog hardware descriptive language and implemented in Field Programmable Gate Array (FPGA). The data access from the SD card is implemented completely using Verilog and hence there is no use of any microcontroller or on-chip general purpose processors. And since the complete design is a single purpose system, no extra hardware is required. The design has four independent modules for the required different operations on the SD memory card. These four modules are for single block write, multiple block write, single block read, and multiple block read operations. A temporary data is either stored internally in an array of registers or externally in the Synchronous RAM for the analysis purposes. The bidirectional access takes place correctly and the data integrity has been verified using Cyclic Redundancy Code in both FPGA processor as well as the SD card controller. The design is implemented on the Altera's Cyclone II EP2C35F672C6 FPGA chip using 1GB SanDisk SD card and has shown a maximum data concentration rate of 25 Mbps.

show abstract

A NAND Flash Memory Controller for SD/MMC Flash Memory Card

Cited by 7 publications

References 9 publications

A Scalable Multi-channel Parallel NAND Flash Memory Controller Architecture

A Scalable Multi-channel Parallel NAND Flash Memory Controller Architecture

Verification and Simulation of New Designed NAND Flash Memory Controller

Data concentration and archival to SD card via hardware description language

Contact Info

Product

Resources

About