In recent years, the use of applications such as artificial intelligence and big data has led to the rise of compute-in-memory signal processing as the primary method for ADC design. Spintronic memory devices, which have non-volatile and low static power consumption characteristics, are particularly well-suited for the design of low-power, high-bandwidth compute-in-memory ADCs. This paper proposes a 3-bit magneto-elastic analog-to-digital converter (MEADC) that comprises eight magnetic tunnel junctions (MTJs), where the MTJ free layer is a bicomponent multiferroic nanomagnet. The bicomponent multiferroic nanomagnet can attain deterministic magnetization switching under zero-field conditions by applying strain-mediated voltage regulation. It has been discovered that there is a linear correlation between the thickness of the piezoelectric layer and the critical flip voltage in a bicomponent multiferroic nanomagnet of a given size and material. Using this principle, the thickness of the piezoelectric layer is adjusted to allow the MEADC to have eight different voltage switching thresholds. This enables the conversion of the analog signal into a combination of different magnetization states of eight multiferroic MTJ. A latch comparator and an independent read circuit are designed to detect the MTJ's resistance state, leading to the output of digital signals. Monte Carlo simulations indicate that the MEADC can achieve a 100% success rate of writing at room temperature. Additionally, the read/write circuits are separated from each other, allowing for the same reference voltage to be set for each MTJ and resulting in higher readability. Micromagnetic simulation and numerical analysis demonstrate that the MEADC can operate at a maximum frequency of 250 MHz, and the energy consumption of a single conversion is only 20 aJ. Compared with the magnetic analog-to-digital converter based on the Racetrack technology, the energy consumption is reduced by 1000 times, and the sampling rate is improved by 10 times. The MEADC proposed in this paper offers an essential technical support for the spintronics-based compute-in-memory integrated circuit architecture.