A Natively Fixed-Point Run-Time Reconfigurable FIR Filter Design Method for FPGA Hardware

Abstract

We present a natively fixed-point filter design method that targets FPGA-based Reconfigurable Finite Impulse Response (RFIR) filters for Software Defined Radio applications. The Filter Designer is capable of reconfiguring cut-off frequencies on-the-fly at run-time; with other parameters, such as filter length and window type, configurable at compile-time. The ability to compute filter coefficients directly on FPGAs is compelling, as much lower latencies can be achieved when compared to RFIRs programmed with embedded processors. In this work we discuss several filter design techniques from the literature and investigate their suitability for implementation on FPGAs. A hybrid method combining window and frequency sampling methods is developed and implemented on a Xilinx Zynq-7000 SoC. We explore the limitations of designing filters in fixed-point arithmetic and consider the effects filter length and wordlength have on filter quality. Results show that the proposed algorithm generates good-quality filters that display stopband attenuation up to 88dB, transition bandwidths less than 1% of the sample rate, and low resource utilisation. Most notably, we found that our method is up to three orders of magnitude faster than an equivalent software implementation, with execution times as low as 2.52 µs, enabling radio applications in which latency is a principal constraint.

A reconfigurable high-speed and low-complexity residue number system-based multiply-accumulate channel filter for software radio receivers

“…The proposed work is further compared with the most recent reported work (Josh Goldsmith et al , 2022), and the results are presented in Table 7. The proposed single MAC RNS filter provides a significant reduction in resource utilization such as LUT usage of 2.13%, the memory requirement of about (BRAM) 1.43% and the number of digital signal processing blocks of about 3.64% when examining with the fixed point runtime filter.…”

“…The moduli sets take a dynamic range, which is used in the RNS scheme and is suitable for the MAC-based filter design (Piestrak and Berezowski, 2008b). The FPGA used the reconfigurable filter design that offers good performance in terms of minimal resource utilization and faster implementation, which is suitable for software radio applications (Josh Goldsmith et al , 2022). The correlative study of the internet of things and its issues are mentioned for present demanding applications reported in Sharma et al (2019).…”

Digital Filter Architecture Based on Modified Winograd Method F(2× 2, 5× 5) and Residue Number System

“…Although the calculation of the filter coefficients according to the given parameters within the device is making the filter more versatile, it requires additional hardware resources [14]. Therefore, it is advisable to calculate the filter coefficients in advance and store them in the device memory.…”