A Network Tearing Technique for FPGA-Based Real-Time Simulation of Power Converters

Ould-Bachir, Tarek; Blanchette, Handy Fortin; Al‐Haddad, Kamal

doi:10.1109/tie.2014.2365752

Cited by 61 publications

(24 citation statements)

References 24 publications

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“…A method to handle diodes has been proposed in [16], but it introduces unrealistic parasitic elements that alter the behavior of the converter. The use of iterations, the compensation method and circuit partitioning have also been considered [17,18], but it results in large time-steps. A predictor-corrector algorithm has been used in [6] to decouple the switches from the circuit elements and to simulate them simultaneously, but such an approach relies on a forward integration scheme and may become unstable.…”

Section: Switch Modelmentioning

confidence: 99%

A Latency-Insensitive Design Approach to Programmable FPGA-Based Real-Time Simulators

2020

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This paper presents a methodology for the design of field-programmable gate array (FPGA)-based real-time simulators (RTSs) for power electronic circuits (PECs). The programmability of the simulator results from the use of an efficient and scalable overlay architecture (OA). The proposed OA relies on a latency-insensitive design (LID) paradigm. LID consists of connecting small processing units that automatically synchronize and exchange data when appropriate. The use of such data-driven architecture aims to ease the design process while achieving a higher computational efficiency. The benefits of the proposed approach is evaluated by assessing the performance of the proposed solver in the simulation of a two-stage AC–AC power converter. The minimum achievable time-step and FPGA resource consumption for a wide range of power converter sizes is also evaluated. The proposed overlays are parametrizable in size, they are cost-effective, they provide sub-microsecond time-steps, and they offer a high computational performance with a reported peak performance of 300 GFLOPS.

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Section: Switch Modelmentioning

confidence: 99%

A Latency-Insensitive Design Approach to Programmable FPGA-Based Real-Time Simulators

2020

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“…Considering the modeling complexity and real‐time simulation step, FPGA‐based models are solved by the Euler algorithm, and CPU‐based models are solved by the RK4 algorithm. The time step of CPU‐based simulation is 20 μs, which can meet the real‐time simulation requirements of fuel cells and supercapacitor …”

Section: Parallel Computing Strategy Of Modular Modelingmentioning

confidence: 99%

“…In HIL simulation, CPUs and field‐programmable gate arrays (FPGAs) provide main hardware platforms that used for real‐time simulation of power electronic systems . FPGA has excellent parallel processing capabilities and very low I/O latency, which make it suitable for real‐time simulation of high frequency power electronic systems . However, its main disadvantages are the programming difficulty and limited hardware resources, which make it difficult to emulate very large‐scale power electronic systems .…”

Section: Introductionmentioning

confidence: 99%

A parallel modular computing approach to real‐time simulation of multiple fuel cells hybrid power system

Zhang

Liu

et al. 2019

Int J Energy Res

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Summary In this paper, a Hardware‐in‐the‐loop (HIL) simulation method for multiple fuel cells hybrid power system based on field‐programmable gate array (FPGA) + CPU architecture is presented. This paper is aiming to propose a parallel modular computing strategy in FPGA, which is used to reduce the programming difficulty and single‐step simulation time. In this strategy, different modules are modeled inside FPGA separately and are connected together to achieve the desired circuit by an interactive connection module. In this way, complex programming is not required when building a system. It only needs a combination of different modules, just like building blocks or modeling in Simulink. This strategy can reduce the programming difficulty greatly when developing complex models in FPGA. Furthermore, it is highly parallelizable to achieve a single‐step simulation time of 0.1 μs in FPGA. The simulation and experimental results demonstrate that the HIL simulation platform has the advantages of high speed, high precision, low cost, and easy to popularize.

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“…In this work, FPGA engine of Opal‐RT is used for simulating plant (electrical circuit) of UPQC D G . FPGA, being fast, offers submicrosecond time steps for simulating fast responding power electronic circuits . CPU core is used for simulating proposed control algorithm with time step of 15 microseconds.…”

Section: Simulation Framework and Case Study Datamentioning

confidence: 99%

“…FPGA, being fast, offers submicrosecond time steps for simulating fast responding power electronic circuits. 23 CPU core is used for simulating proposed control algorithm with time step of 15 microseconds. Control unit of UPQC DG , implemented on CPU core, receives measurements from electrical circuit, which runs on FPGA.…”

Section: Simulation Frameworkmentioning

confidence: 99%

A new SRF-based power angle control method for UPQC-DG to integrate solar PV into grid

Patel

Mathur

Bhanot

2018

Int Trans Electr Energ Syst

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Summary In this paper, a new synchronous reference frame theory–based power angle control (PAC) method for unified power quality conditioner with distributed generation (UPQCDG) is proposed for effective grid integration of solar PV. In UPQCDG, shunt active power filter (APF) feeds power from distributed generator to load, apart from supplying reactive power demand, which leads to increase in VA burden, hence its rating. Power angle control method aims at effective utilization of series and shunt APFs through sharing of reactive power to reduce VA burden on shunt APF. Proposed PAC method is based on instantaneous three‐phase power estimation technique, which is simple and robust and utilizes already available measurements of UPQCDG. Performance of proposed system is tested in the presence of nonlinear and reactive loads with solar PV generation system. Dynamic performance of system is studied during grid disturbances such as voltage sag and swell, solar irradiation variation, and change in load. Effectiveness of proposed method is validated using real‐time simulation performed in Opal‐RT, in which electrical circuit of UPQCDG is simulated on FPGA computation engine with submicrosecond time step to emulate real hardware closely.

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A Network Tearing Technique for FPGA-Based Real-Time Simulation of Power Converters

Cited by 61 publications

References 24 publications

A Latency-Insensitive Design Approach to Programmable FPGA-Based Real-Time Simulators

A Latency-Insensitive Design Approach to Programmable FPGA-Based Real-Time Simulators

A parallel modular computing approach to real‐time simulation of multiple fuel cells hybrid power system

A new SRF-based power angle control method for UPQC-DG to integrate solar PV into grid

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