A Network Traffic Generator Model for Fast Network-on-Chip Simulation

Mahadevan, Shankar; Angiolini, Federico; Sparsø, Jens; Storgaard, Michael; Madsen, Jan; Olsen, Rasmus Grondahl

doi:10.1007/978-1-4020-6488-3_13

Design, Automation, and Test in Europe 2008

DOI: 10.1007/978-1-4020-6488-3_13

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A Network Traffic Generator Model for Fast Network-on-Chip Simulation

Shankar Mahadevan

Federico Angiolini

Jens Sparsø

et al.

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2016

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“…In modern research, reducing the data access latency and energy consumption in the NoC design plays a vital role. If the traffic is generated, the time constraint increases the energy consumption [10]. The generic traffic model is used to analyze the traffic characteristics of on-chip interconnection application specific network.…”

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confidence: 99%

FSM Based DFS Link for Network on Chip

Sakthivel¹,

Veeraraghavan²,

Arunraja³

et al. 2016

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As low power consumption is the main design issue involved in a network on chip (NoC), researchers are concentrating more on both algorithms and architectural approaches. The conventional Dynamic Frequency Scaling (DFS) and history based Frequency Scaling (HDFS) algorithms are utilized to process the energy constrained data traffic. However, these conventional algorithms achieve higher energy efficiencies, and they result in performance degradation due to the auxiliary latency between clock domains. In this paper, we present a variable power optimization interface for NoC using a Finite State Machine (FSM) approach to attain better performance improvement. The parameters are estimated using 45 nm TSMC CMOS technology. In comparison with DFS system, the evaluation results show that FSM-DFS link achieves 81.55% dynamic power savings on the links in the on-chip network, and 37.5% leakage power savings of the link. Also, this proposed work is evaluated for various performance parameters and compared with conventional work. The simulation results are superior to conventional work. Keywords Network-on-Chip (NoC), Dynamic Frequency Scaling (DFS), Finite State Machines (FSM)How to cite this paper: Sakthivel, E., Malathi, V., Arunraja, M. and Perumalvignesh, G. (2016) FSM Based DFS Link for Network on Chip. Circuits and Systems, 7, 1734-1750. http://dx.doi.org/10.4236/cs.2016.78150 E. Sakthivel et al. achieve peak performance of 1.0TFLOPS at 1 V, while dissipating 98 w [3].In [4], the Tile 64 processor design considerations such as arbitration, topology and length of physical links, width of physical links, buffer allocation, switching techniques, routing algorithms, and levels of service are addressed in the NoC core. This architectural challenge through "tiled" architecture can be connected by scalable and energy-efficient architecture.In general, the NoC architecture provides performance degradation by means of more scalability and high power consumption [5]. To achieve lower power consumption and a high operating speed, designers prefer the Dynamic Voltage and Frequency Scaling algorithm (DVFS) [6]. To avoid this complication, History based Dynamic Frequency Scaling (H-DFS) is introduced by Lee et al. [7]. In [8], Dynamic Voltage Scaling algorithm (DVS) implemented in a scalable architecture is developed by external circuit combinations of system configurations. The existing low power algorithms are used to reduce power consumption by adjusting the power mode of the links to match the traffic flows. These algorithms fail to act on sudden traffic changes. To overcome this issue, a novel application-driven approach for predicting traffic described in [9]. Here, a novel data structure called Application Traffic Prediction Table (ATPT) is used to record the core's outgoing messages (traffic) and the DFS policy is applied to the link. Conventional traffic generation is a novel structural design template that yields a complicated system level design [9]. In modern research, reducing the data access latency and energy consum...

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mentioning

confidence: 99%

FSM Based DFS Link for Network on Chip

Sakthivel¹,

Veeraraghavan²,

Arunraja³

et al. 2016

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A Network Traffic Generator Model for Fast Network-on-Chip Simulation

Cited by 1 publication

References 9 publications

FSM Based DFS Link for Network on Chip

FSM Based DFS Link for Network on Chip

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